[FireSim] Use black-box instantiations of endpoints

generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala

@@ -0,0 +1,72 @@
+package firesim.firesim
+
+import chisel3._
+import chisel3.experimental.RawModule
+
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
+import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
+
+import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
+
+import junctions.{NastiKey, NastiParameters}
+import midas.widgets.{IsEndpoint, PeekPokeEndpoint}
+import midas.models.{FASEDEndpoint, FasedAXI4Edge}
+import firesim.endpoints._
+import firesim.configs.MemModelKey
+
+// Creates a wrapper module that instantiates endpoints based on the scala type
+// of the Target (_not_ its IO). This avoids needing to duplicate environments
+// (essentially test harnesses) for each target type,
+//
+// You could just as well create a custom environment (essentially, test
+// harness) module that instantiates endpoints explicitly, or add methods to
+// your target traits that instantiate the endpoint there (i.e., akin to
+// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match
+// on the types rather than change trait code.
+
+class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule {
+  val clock = IO(Input(Clock()))
+  val reset = WireInit(false.B)
+  withClockAndReset(clock, reset) {
+    val target = Module(LazyModule(dutGen()).module)
+    val peekPokeEndpoint = PeekPokeEndpoint(reset)
+    // A Seq of partial functions that will instantiate the right endpoint only
+    // if that Mixin trait is present in the target's class instance
+    //
+    // TODO: If we like this PF approach, register them in the config instead of centralizing them here
+    val endpointBinders = Seq[PartialFunction[Any, Seq[IsEndpoint]]](
+      { case t: HasPeripheryDebugModuleImp =>
+        t.debug.clockeddmi.foreach({ cdmi =>
+          cdmi.dmi.req.valid := false.B
+          cdmi.dmi.req.bits := DontCare
+          cdmi.dmi.resp.ready := false.B
+          cdmi.dmiClock := false.B.asClock
+          cdmi.dmiReset := false.B
+        })
+        Seq()
+      },
+      { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) },
+      { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) },
+      { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) },
+      { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp =>
+        (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
+          (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
+            val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
+                                           axi4Bundle.ar.bits.addr.getWidth,
+                                           axi4Bundle.ar.bits.id.getWidth)
+            val fasedP = p.alterPartial({
+              case NastiKey => nastiKey
+              case FasedAXI4Edge => Some(edge)
+            })
+            FASEDEndpoint(axi4Bundle, reset, p(MemModelKey)(fasedP))(fasedP)
+          })
+        }).toSeq
+      },
+      { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) }
+    )
+    // Apply each partial function to the DUT; collecting the generated endpoints
+    val endpoints = endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target))
+  }
+}

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -14,7 +14,6 @@ import testchipip.{BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import icenet._
 
-import firesim.util.{EndpointKey, TieOffDebug}
 import firesim.endpoints._
 import firesim.configs.WithDefaultMemModel
 
@@ -37,33 +36,15 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
 })
 
 class WithUARTKey extends Config((site, here, up) => {
-  case EndpointKey => up(EndpointKey) ++ Seq(UARTEndpoint)
   case PeripheryUARTKey => List(UARTParams(
      address = BigInt(0x54000000L),
      nTxEntries = 256,
      nRxEntries = 256))
 })
 
-class WithSerialEndpoint extends Config((site, here, up) => {
+class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
-  case EndpointKey => up(EndpointKey) ++ Seq(SerialEndpoint)
-})
-
-class WithTracerVEndpoint extends Config((site, here, up) => {
-  case EndpointKey => up(EndpointKey) ++ Seq(TracerVEndpoint)
-})
-
-class WithBlockDevice extends Config(
-  new Config((site, here, up) => {
-    case EndpointKey => up(EndpointKey) ++ Seq(BlockDevEndpoint, firesim.util.FASEDEndpointMatcher)
-  }) ++ new testchipip.WithBlockDevice
-)
-
-class WithTieOffDebug extends Config((site, here, up) => {
-  case EndpointKey => up(EndpointKey) ++ Seq(TieOffDebug)
-})
 
 class WithNICKey extends Config((site, here, up) => {
-  //case EndpointKey => up(EndpointKey) ++ Seq(NICEndpoint)
   case NICKey => NICConfig(
     inBufFlits = 8192,
     ctrlQueueDepth = 64)
@@ -122,9 +103,6 @@ class FireSimRocketChipConfig extends Config(
   new WithPerfCounters ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++
-  new WithSerialEndpoint ++
-  new WithTracerVEndpoint ++
-  new WithTieOffDebug ++
   new freechips.rocketchip.system.DefaultConfig)
 
 class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
@@ -165,9 +143,6 @@ class FireSimBoomConfig extends Config(
   new WithBoomL2TLBs(1024) ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++
-  new WithSerialEndpoint ++
-  new WithTracerVEndpoint ++
-  new WithTieOffDebug ++
   // Using a small config because it has 64-bit system bus, and compiles quickly
   new boom.system.SmallBoomConfig)
 

generators/firechip/src/main/scala/Targets.scala

@@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.amba.axi4.AXI4Bundle
@@ -16,15 +17,14 @@ import icenet._
 import testchipip._
 import testchipip.SerialAdapter.SERIAL_IF_WIDTH
 import sifive.blocks.devices.uart._
-import midas.models.AXI4BundleWithEdge
-import firesim.util.IOMatchingMIDASEnvironment
 import java.io.File
 
 
 object FireSimValName {
-  implicit val valName = ValName("TestHarness")
+  implicit val valName = ValName("FireSimHarness")
 }
 import FireSimValName._
+
 /*******************************************************************************
 * Top level DESIGN configurations. These describe the basic instantiations of
 * the designs being simulated.
@@ -40,7 +40,6 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
     with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasNoDebug
     with HasPeripherySerial
     with HasPeripheryUART
     with HasPeripheryIceNIC
@@ -54,7 +53,6 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripheryIceNICModuleImpValidOnly
@@ -62,13 +60,10 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(
     with HasTraceIOImp
     with CanHaveRocketMultiCycleRegfileImp
 
-class FireSim(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimDUT).module)
-
 class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
     with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasNoDebug
     with HasPeripherySerial
     with HasPeripheryUART
     with HasPeripheryBlockDevice
@@ -81,7 +76,6 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
@@ -89,13 +83,12 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem
     with CanHaveRocketMultiCycleRegfileImp
 
 
-class FireSimNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimNoNICDUT).module)
+class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT)
 
 class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
     with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasNoDebug
     with HasPeripherySerial
     with HasPeripheryUART
     with HasPeripheryIceNIC
@@ -109,7 +102,6 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripheryIceNICModuleImpValidOnly
@@ -118,13 +110,10 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu
     with ExcludeInvalidBoomAssertions
     with CanHaveBoomMultiCycleRegfileImp
 
-class FireBoom(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomDUT).module)
-
 class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
     with HasDefaultBusConfiguration
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasNoDebug
     with HasPeripherySerial
     with HasPeripheryUART
     with HasPeripheryBlockDevice
@@ -137,7 +126,6 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
@@ -145,14 +133,12 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub
     with ExcludeInvalidBoomAssertions
     with CanHaveBoomMultiCycleRegfileImp
 
-class FireBoomNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomNoNICDUT).module)
-
 case object NumNodes extends Field[Int]
 
 class SupernodeIO(
       nNodes: Int,
       serialWidth: Int,
-      bagPrototype: HeterogeneousBag[AXI4BundleWithEdge])(implicit p: Parameters)
+      bagPrototype: HeterogeneousBag[midas.models.AXI4BundleWithEdge])(implicit p: Parameters)
     extends Bundle {
 
     val serial = Vec(nNodes, new SerialIO(serialWidth))
@@ -190,5 +176,3 @@ class FireSimSupernodeDUT(implicit p: Parameters) extends Module {
     n.debug.clockeddmi.get.dmi.req.bits.op := DontCare
   } }
 }
-
-class FireSimSupernode(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => new FireSimSupernodeDUT)