From e27f1a3195a4c8d67ca5509458b251f19330b411 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Sat, 4 Feb 2023 16:17:02 -0800
Subject: [PATCH] Make SpikeTile ipc a plusarg

---
 generators/chipyard/src/main/scala/SpikeTile.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index 44a6229a..cc83a46c 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -16,7 +16,6 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.prci.ClockSinkParameters
 
 case class SpikeCoreParams(
-  val maxInsnsPerCycle: Int = 10000
 ) extends CoreParams {
   val useVM = true
   val useHypervisor = false
@@ -305,7 +304,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   spike.io.msip := int_bundle.msip
   spike.io.meip := int_bundle.meip
   spike.io.seip := int_bundle.seip.get
-  spike.io.ipc := outer.spikeTileParams.core.maxInsnsPerCycle.U
+  spike.io.ipc := PlusArg("spike-ipc", 10000, width=64)
 
   val blockBits = log2Ceil(p(CacheBlockBytes))
   spike.io.icache.a.ready := icache_tl.a.ready