From b386e145d478e2ad41c911210b3c7d7cc33bb1c2 Mon Sep 17 00:00:00 2001 From: JL102 Date: Fri, 3 Nov 2023 19:06:23 -0400 Subject: [PATCH 1/2] docs: Add info on chipyard's tests dir The most important part of this addition, IMO, is the note about `__main()`, since it's currently not noted anywhere in Chipyard's docs. It was initially very hard for me to find any explanation about __main until I stumbled across libgloss-htif's readme page. Signed-off-by: JL102 --- docs/Simulation/Software-RTL-Simulation.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 2e832182..68ebd541 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -81,6 +81,24 @@ For example: .. _sw-sim-custom: +Custom Benchmarks/Tests +------------------------------- + +To compile your own code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. Then when you run ``make``, all of the programs inside ``tests`` will output a ``.riscv`` binary, which can be used with the simulator as described above. + +.. code-block:: shell + + # Enter Tests directory + cd tests + make + + # Enter Verilator or VCS directory + cd ../sims/verilator + make run-binary BINARY=../../tests/hello.riscv + +.. Note:: On multi-core configurations, only hart (**har**\ dware **t**\ hread) 0 executes the ``main()`` function. All other harts execute the secondary ``__main()`` function, which defaults to a busy loop. To run a multi-threaded workload on a Verilator/VCS simulation, override ``__main()`` with your own code. More details can be found `here `_ + + Makefile Variables and Commands ------------------------------- You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``: From 5136b7e2ead148e58e6051c8355bb785b9132f8f Mon Sep 17 00:00:00 2001 From: Jordan Lees Date: Fri, 3 Nov 2023 23:56:51 -0400 Subject: [PATCH 2/2] Update docs/Simulation/Software-RTL-Simulation.rst Co-authored-by: Jerry Zhao --- docs/Simulation/Software-RTL-Simulation.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 68ebd541..8c87cc80 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -84,7 +84,7 @@ For example: Custom Benchmarks/Tests ------------------------------- -To compile your own code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. Then when you run ``make``, all of the programs inside ``tests`` will output a ``.riscv`` binary, which can be used with the simulator as described above. +To compile your own bare-metal code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. These binaries are compiled with the libgloss-htif library, which implements a minimal set of useful syscalls for bare-metal binaries. Then when you run ``make``, all of the programs inside ``tests`` will be compiled into ``.riscv`` ELF binaries, which can be used with the simulator as described above. .. code-block:: shell