wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Remove chisel-testers submodule

Browse Source
This commit is contained in:
abejgonzalez
2023-03-03 16:50:00 -08:00
committed by joey0320
parent 3a53dc60d0
commit e3424f7193
5 changed files with 1 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
docs/Tools/Chisel-Testers.rst
View File

@@ -1,7 +0,0 @@
Chisel Testers
==============================
`Chisel Testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs.
It provides a Scala API for interacting with a DUT.
It can use multiple backends, including things such as Treadle and Verilator.
See :ref:`Tools/Treadle:Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods.

1
docs/Tools/index.rst
View File

@@ -11,7 +11,6 @@ The following pages will introduce them, and how we can use them in order to gen
Chisel
FIRRTL
Treadle
Chisel-Testers
Dsptools
Barstools
Dromajo