diff --git a/generators/boom b/generators/boom index 4e9d496d..793912ee 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4e9d496d3678cc5ae005669a448ae9e89f8ae847 +Subproject commit 793912eef8a9f09c13bd791c33ba682350a6026a diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala index f328b902..c97154aa 100644 --- a/generators/example/src/main/scala/BoomConfigs.scala +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -3,88 +3,65 @@ package example import chisel3._ import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{WithJtagDTM} - -import boom.common._ // --------------------- // BOOM Configs // --------------------- class SmallBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.SmallBoomConfig) + new WithTop ++ // use normal top + new WithBootROM ++ // use testchipip bootrom + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new boom.common.WithSmallBooms ++ // 1-wide BOOM + new boom.common.WithNBoomCores(1) ++ // single-core + new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system class MediumBoomConfig extends Config( - new WithNormalBoomRocketTop ++ + new WithTop ++ new WithBootROM ++ - new boom.common.MediumBoomConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithMediumBooms ++ // 2-wide BOOM + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( - new WithNormalBoomRocketTop ++ + new WithTop ++ new WithBootROM ++ - new boom.common.LargeBoomConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithLargeBooms ++ // 3-wide BOOM + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( - new WithNormalBoomRocketTop ++ + new WithTop ++ new WithBootROM ++ - new boom.common.MegaBoomConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithMegaBooms ++ // 4-wide BOOM + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) -class jtagSmallBoomConfig extends Config( - new WithDTMBoomRocketTop ++ +class DualSmallBoomConfig extends Config( + new WithTop ++ new WithBootROM ++ - new WithJtagDTM ++ - new boom.common.SmallBoomConfig) - -class jtagMediumBoomConfig extends Config( - new WithDTMBoomRocketTop ++ - new WithBootROM ++ - new WithJtagDTM ++ - new boom.common.MediumBoomConfig) - -class jtagLargeBoomConfig extends Config( - new WithDTMBoomRocketTop ++ - new WithBootROM ++ - new WithJtagDTM ++ - new boom.common.LargeBoomConfig) - -class jtagMegaBoomConfig extends Config( - new WithDTMBoomRocketTop ++ - new WithBootROM ++ - new WithJtagDTM ++ - new boom.common.MegaBoomConfig) - -class SmallDualBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.SmallDualBoomConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithSmallBooms ++ + new boom.common.WithNBoomCores(2) ++ // dual-core + new freechips.rocketchip.system.BaseConfig) class TracedSmallBoomConfig extends Config( - new WithNormalBoomRocketTop ++ + new WithTop ++ new WithBootROM ++ - new boom.common.TracedSmallBoomConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithTrace ++ // enable trace port on BOOM + new boom.common.WithSmallBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class SmallRV32UnifiedBoomConfig extends Config( - new WithNormalBoomRocketTop ++ + new WithTop ++ new WithBootROM ++ - new boom.common.SmallRV32UnifiedBoomConfig) - -// -------------------------- -// BOOM + Rocket Configs -// -------------------------- - -class SmallBoomAndRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.SmallBoomAndRocketConfig) - -class MediumBoomAndRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.MediumBoomAndRocketConfig) - -class DualMediumBoomAndDualRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.DualMediumBoomAndDualRocketConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithUnifiedMemIntIQs ++ // use unified mem+int issue queues + new boom.common.WithSmallBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 17fac94d..17cbcaa5 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC} -import boom.system.{BoomTilesKey} +import boom.common.{BoomTilesKey} import testchipip._ @@ -52,43 +52,43 @@ class WithGPIO extends Config((site, here, up) => { /** * Class to specify a "plain" top level BOOM and/or Rocket system */ -class WithNormalBoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomRocketTop()(p)).module) +class WithTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new Top()(p)).module) } }) /** * Class to specify a top level BOOM and/or Rocket system with DTM */ -class WithDTMBoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomRocketTopWithDTM()(p)).module) +class WithDTMTop extends Config((site, here, up) => { + case BuildTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new TopWithDTM()(p)).module) } }) /** * Class to specify a top level BOOM and/or Rocket system with PWM */ -class WithPWMBoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module) +class WithPWMTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new TopWithPWMTL()(p)).module) }) /** * Class to specify a top level BOOM and/or Rocket system with a PWM AXI4 */ -class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module) +class WithPWMAXI4Top extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new TopWithPWMAXI4()(p)).module) }) /** * Class to specify a top level BOOM and/or Rocket system with a block device */ -class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) +class WithBlockDeviceModelTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new TopWithBlockDevice()(p)).module) top.connectBlockDeviceModel() top } @@ -97,9 +97,9 @@ class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => { /** * Class to specify a top level BOOM and/or Rocket system with a simulator block device */ -class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) +class WithSimBlockDeviceTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new TopWithBlockDevice()(p)).module) top.connectSimBlockDevice(clock, reset) top } @@ -108,9 +108,9 @@ class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => { /** * Class to specify a top level BOOM and/or Rocket system with GPIO */ -class WithGPIOBoomRocketTop extends Config((site, here, up) => { - case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module) +class WithGPIOTop extends Config((site, here, up) => { + case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new TopWithGPIO()(p)).module) for (gpio <- top.gpio) { for (pin <- gpio.pins) { pin.i.ival := false.B diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index c7e70dd2..5004e6ee 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -3,264 +3,100 @@ package example import chisel3._ import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache} - -import testchipip._ // -------------- // Rocket Configs // -------------- -class BaseRocketConfig extends Config( +class RocketConfig extends Config( + new WithTop ++ // use default top + new WithBootROM ++ // use default bootrom + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system (implicitly creates Rocket cores) + +class HwachaRocketConfig extends Config( + new WithTop ++ new WithBootROM ++ - new freechips.rocketchip.system.DefaultConfig) - -class DefaultRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new BaseRocketConfig) - -class HwachaConfig extends Config( - new hwacha.DefaultHwachaConfig ++ - new DefaultRocketConfig) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class RoccRocketConfig extends Config( - new WithRoccExample ++ - new DefaultRocketConfig) + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class jtagRocketConfig extends Config( + new WithDTMTop ++ // use top with dtm + new freechips.rocketchip.subsystem.WithJtagDTM ++ // add jtag/DTM module to coreplex + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class PWMRocketConfig extends Config( - new WithPWMBoomRocketTop ++ - new BaseRocketConfig) + new WithPWMTop ++ // use top with tilelink-controlled PWM + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) -class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4BoomRocketTop ++ - new BaseRocketConfig) +class PWMRAXI4ocketConfig extends Config( + new WithPWMAXI4Top ++ // use top with axi4-controlled PWM + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class SimBlockDeviceRocketConfig extends Config( - new WithBlockDevice ++ - new WithSimBlockDeviceBoomRocketTop ++ - new BaseRocketConfig) + new testchipip.WithBlockDevice ++ // add block-device module to peripherybus + new WithSimBlockDeviceTop ++ // use top with block-device IOs and connect to simblockdevice + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( - new WithBlockDevice ++ - new WithBlockDeviceModelBoomRocketTop ++ - new BaseRocketConfig) + new testchipip.WithBlockDevice ++ // add block-device module to periphery bus + new WithBlockDeviceModelTop ++ // use top with block-device IOs and connect to a blockdevicemodel + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class GPIORocketConfig extends Config( - new WithGPIO ++ - new WithGPIOBoomRocketTop ++ - new BaseRocketConfig) + new WithGPIO ++ // add GPIOs to the peripherybus + new WithGPIOTop ++ // use top with GPIOs + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) class DualCoreRocketConfig extends Config( - new WithNBigCores(2) ++ - new DefaultRocketConfig) + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles) + new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( - new WithRV32 ++ - new DefaultRocketConfig) - -class GB1MemoryConfig extends Config( - new WithExtMemSize((1<<30) * 1L) ++ - new DefaultRocketConfig) - -class RocketL2Config extends Config( - new WithInclusiveCache ++ - new DefaultRocketConfig) - -class HwachaL2Config extends Config( - new hwacha.DefaultHwachaConfig ++ - new WithInclusiveCache ++ - new DefaultRocketConfig) - -// ------------ -// BOOM Configs -// ------------ - -class BaseBoomConfig extends Config( + new WithTop ++ new WithBootROM ++ - new boom.common.LargeBoomConfig) - -class SmallBaseBoomConfig extends Config( - new WithBootROM ++ - new boom.common.SmallBoomConfig) - -class DefaultBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new BaseBoomConfig) - -class SmallDefaultBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new SmallBaseBoomConfig) - -class HwachaBoomConfig extends Config( - new hwacha.DefaultHwachaConfig ++ - new DefaultBoomConfig) - -class RoccBoomConfig extends Config( - new WithRoccExample ++ - new DefaultBoomConfig) - -class PWMBoomConfig extends Config( - new WithPWMBoomRocketTop ++ - new BaseBoomConfig) - -class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomRocketTop ++ - new BaseBoomConfig) - -class SimBlockDeviceBoomConfig extends Config( - new WithBlockDevice ++ - new WithSimBlockDeviceBoomRocketTop ++ - new BaseBoomConfig) - -class BlockDeviceModelBoomConfig extends Config( - new WithBlockDevice ++ - new WithBlockDeviceModelBoomRocketTop ++ - new BaseBoomConfig) - -class GPIOBoomConfig extends Config( - new WithGPIO ++ - new WithGPIOBoomRocketTop ++ - new BaseBoomConfig) - -/** - * Slightly different looking configs since we need to override - * the `WithNBoomCores` with the DefaultBoomConfig params - */ -class DualCoreBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.WithRVC ++ - new boom.common.WithLargeBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(2) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.system.BaseConfig) - -class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.WithRVC ++ - new boom.common.WithSmallBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(2) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.system.BaseConfig) - -class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.SmallRV32UnifiedBoomConfig) - -class BoomL2Config extends Config( - new WithInclusiveCache ++ - new SmallDefaultBoomConfig) - -// --------------------- -// BOOM and Rocket Configs -// --------------------- - -class BaseBoomAndRocketConfig extends Config( - new WithBootROM ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithRVC ++ - new boom.common.WithLargeBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -class SmallBaseBoomAndRocketConfig extends Config( +class GB1MemoryRocketConfig extends Config( + new WithTop ++ new WithBootROM ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithRVC ++ - new boom.common.WithSmallBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 2GB simulated external memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -class DefaultBoomAndRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new BaseBoomAndRocketConfig) - -class SmallDefaultBoomAndRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new SmallBaseBoomAndRocketConfig) - -class HwachaBoomAndRocketConfig extends Config( - new hwacha.DefaultHwachaConfig ++ - new DefaultBoomAndRocketConfig) - -class RoccBoomAndRocketConfig extends Config( - new WithRoccExample ++ - new DefaultBoomAndRocketConfig) - -class PWMBoomAndRocketConfig extends Config( - new WithPWMBoomRocketTop ++ - new BaseBoomAndRocketConfig) - -class PWMAXI4BoomAndRocketConfig extends Config( - new WithPWMAXI4BoomRocketTop ++ - new BaseBoomAndRocketConfig) - -class SimBlockDeviceBoomAndRocketConfig extends Config( - new WithBlockDevice ++ - new WithSimBlockDeviceBoomRocketTop ++ - new BaseBoomAndRocketConfig) - -class BlockDeviceModelBoomAndRocketConfig extends Config( - new WithBlockDevice ++ - new WithBlockDeviceModelBoomRocketTop ++ - new BaseBoomAndRocketConfig) - -class GPIOBoomAndRocketConfig extends Config( - new WithGPIO ++ - new WithGPIOBoomRocketTop ++ - new BaseBoomAndRocketConfig) - -class DualCoreBoomAndOneRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithRVC ++ - new boom.common.WithLargeBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(2) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - -class DualBoomAndOneHwachaRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new WithMultiRoCC ++ - new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket - new boom.common.WithRenumberHarts(rocketFirst = true) ++ - new hwacha.DefaultHwachaConfig ++ - new boom.common.WithRVC ++ - new boom.common.WithLargeBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(2) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - -class RV32BoomAndRocketConfig extends Config( - new WithNormalBoomRocketTop ++ - new WithBootROM ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithBoomRV32 ++ - new boom.common.WithRVC ++ - new boom.common.WithLargeBooms ++ - new boom.common.BaseBoomConfig ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new freechips.rocketchip.subsystem.WithRV32 ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - -class DualCoreRocketL2Config extends Config( - new WithInclusiveCache ++ - new DualCoreRocketConfig) diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/example/src/main/scala/HeteroConfigs.scala new file mode 100644 index 00000000..898991d7 --- /dev/null +++ b/generators/example/src/main/scala/HeteroConfigs.scala @@ -0,0 +1,84 @@ +package example + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +// --------------------- +// Heterogenous Configs +// --------------------- + +class LargeBoomAndRocketConfig extends Config( + new WithTop ++ // default top + new WithBootROM ++ // default bootrom + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive l2 + new boom.common.WithRenumberHarts ++ // avoid hartid overlap + new boom.common.WithLargeBooms ++ // 3-wide boom + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket + new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system + +class HwachaLargeBoomAndHwachaRocketConfig extends Config( + new WithTop ++ + new WithBootROM ++ + new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class RoccLargeBoomAndRoccRocketConfig extends Config( + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithRoccExample ++ // add example rocc accelerator to all harts + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class DualLargeBoomAndRocketConfig extends Config( + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(2) ++ // 2-boom cores + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class DualLargeBoomAndHwachaRocketConfig extends Config( + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new WithMultiRoCC ++ // support heterogeneous rocc + new WithMultiRoCCHwacha(2) ++ // put hwacha on hart-2 (rocket) + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class LargeBoomAndRV32RocketConfig extends Config( + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithRV32 ++ // use 32-bit rocket + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class DualLargeBoomAndDualRocketConfig extends Config( + new WithTop ++ + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/example/src/main/scala/Subsystem.scala b/generators/example/src/main/scala/Subsystem.scala new file mode 100644 index 00000000..7888bc4f --- /dev/null +++ b/generators/example/src/main/scala/Subsystem.scala @@ -0,0 +1,108 @@ +//****************************************************************************** +// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents). +// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. +//------------------------------------------------------------------------------ + +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} +import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey} + + +trait HasBoomAndRocketTiles extends HasTiles + with CanHavePeripheryPLIC + with CanHavePeripheryCLINT + with HasPeripheryDebug +{ this: BaseSubsystem => + + val module: HasBoomAndRocketTilesModuleImp + + protected val rocketTileParams = p(RocketTilesKey) + protected val boomTileParams = p(BoomTilesKey) + // crossing can either be per tile or global (aka only 1 crossing specified) + private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) + private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) + + // Make a tile and wire its nodes into the system, + // according to the specified type of clock crossing. + // Note that we also inject new nodes into the tile itself, + // also based on the crossing type. + val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => + val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) + + connectMasterPortsToSBus(rocket, crossing) + connectSlavePortsToCBus(rocket, crossing) + + def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets) + LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree) + + rocket + } + + val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => + val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) + + connectMasterPortsToSBus(boom, crossing) + connectSlavePortsToCBus(boom, crossing) + + def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets) + LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree) + + boom + } + + // combine tiles and connect interrupts based on the order of harts + val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map { + tile => { + connectInterrupts(tile, Some(debug), clintOpt, plicOpt) + + tile + } + } + + def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ + (boomTiles map { t => t.module.core.coreMonitorBundle}).toList +} + +trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp + with HasPeripheryDebugModuleImp +{ + val outer: HasBoomAndRocketTiles +} + +class Subsystem(implicit p: Parameters) extends BaseSubsystem + with HasBoomAndRocketTiles +{ + val tiles = boomAndRocketTiles + override lazy val module = new SubsystemModuleImp(this) + + def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil +} + +class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) + with HasResetVectorWire + with HasBoomAndRocketTilesModuleImp +{ + tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => + wire.hartid := i.U + wire.reset_vector := global_reset_vector + } + + // create file with boom params + ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) +} diff --git a/generators/example/src/main/scala/System.scala b/generators/example/src/main/scala/System.scala new file mode 100644 index 00000000..1c62bf51 --- /dev/null +++ b/generators/example/src/main/scala/System.scala @@ -0,0 +1,63 @@ +//****************************************************************************** +// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents). +// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. +//------------------------------------------------------------------------------ + +package example + +import chisel3._ + +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.util.{DontTouch} + +// --------------------------------------------------------------------- +// Base system that uses the debug test module (dtm) to bringup the core +// --------------------------------------------------------------------- + +/** + * Base top with periphery devices and ports, and a BOOM + Rocket subsystem + */ +class System(implicit p: Parameters) extends Subsystem + with HasAsyncExtInterrupts + with CanHaveMasterAXI4MemPort + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port + with HasPeripheryBootROM +{ + override lazy val module = new SystemModule(this) + + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + +/** + * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem + */ +class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with CanHaveMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MMIOPortModuleImp + with CanHaveSlaveAXI4PortModuleImp + with HasPeripheryBootROMModuleImp + with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 778fcc81..61807f2e 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -14,8 +14,8 @@ import freechips.rocketchip.devices.debug.{Debug} // BOOM and/or Rocket Test Harness // ------------------------------- -case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] -case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]] +case object BuildTop extends Field[(Clock, Bool, Parameters) => TopModule[Top]] +case object BuildTopWithDTM extends Field[(Clock, Bool, Parameters) => TopWithDTMModule[TopWithDTM]] /** * Test harness using TSI to bringup the system @@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module { // force Chisel to rename module override def desiredName = "TestHarness" - val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) + val dut = p(BuildTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() @@ -63,7 +63,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module // force Chisel to rename module override def desiredName = "TestHarness" - val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p) + val dut = p(BuildTopWithDTM)(clock, reset.toBool, p) dut.reset := reset.asBool | dut.debug.ndreset dut.connectSimAXIMem() diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index b861fdec..bfb03e0c 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -16,63 +16,63 @@ import sifive.blocks.devices.gpio._ // BOOM and/or Rocket Top Level Systems // ------------------------------------ -class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem +class Top(implicit p: Parameters) extends System with HasNoDebug with HasPeripherySerial { - override lazy val module = new BoomRocketTopModule(this) + override lazy val module = new TopModule(this) } -class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.BoomRocketSystemModule(l) +class TopModule[+L <: Top](l: L) extends SystemModule(l) with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch //--------------------------------------------------------------------------------------------------------- -class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop +class TopWithPWMTL(implicit p: Parameters) extends Top with HasPeripheryPWMTL { - override lazy val module = new BoomRocketTopWithPWMTLModule(this) + override lazy val module = new TopWithPWMTLModule(this) } -class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l) +class TopWithPWMTLModule(l: TopWithPWMTL) extends TopModule(l) with HasPeripheryPWMTLModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop +class TopWithPWMAXI4(implicit p: Parameters) extends Top with HasPeripheryPWMAXI4 { - override lazy val module = new BoomRocketTopWithPWMAXI4Module(this) + override lazy val module = new TopWithPWMAXI4Module(this) } -class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l) +class TopWithPWMAXI4Module(l: TopWithPWMAXI4) extends TopModule(l) with HasPeripheryPWMAXI4ModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop +class TopWithBlockDevice(implicit p: Parameters) extends Top with HasPeripheryBlockDevice { - override lazy val module = new BoomRocketTopWithBlockDeviceModule(this) + override lazy val module = new TopWithBlockDeviceModule(this) } -class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l) +class TopWithBlockDeviceModule(l: TopWithBlockDevice) extends TopModule(l) with HasPeripheryBlockDeviceModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop - with HasPeripheryGPIO { - override lazy val module = new BoomRocketTopWithGPIOModule(this) +class TopWithGPIO(implicit p: Parameters) extends Top + with HasPeripheryGPIO { + override lazy val module = new TopWithGPIOModule(this) } -class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) - extends BoomRocketTopModule(l) +class TopWithGPIOModule(l: TopWithGPIO) + extends TopModule(l) with HasPeripheryGPIOModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem +class TopWithDTM(implicit p: Parameters) extends System { - override lazy val module = new BoomRocketTopWithDTMModule(this) + override lazy val module = new TopWithDTMModule(this) } -class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l) +class TopWithDTMModule[+L <: TopWithDTM](l: L) extends SystemModule(l) diff --git a/generators/utilities/src/main/scala/TestSuites.scala b/generators/utilities/src/main/scala/TestSuites.scala index ab0ff8d5..725e1e69 100644 --- a/generators/utilities/src/main/scala/TestSuites.scala +++ b/generators/utilities/src/main/scala/TestSuites.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} -import boom.system.{BoomTilesKey} +import boom.common.{BoomTilesKey} /** * A set of pre-chosen regression tests diff --git a/variables.mk b/variables.mk index ca0f8fc9..ddf05da8 100644 --- a/variables.mk +++ b/variables.mk @@ -32,11 +32,11 @@ ifeq ($(SUB_PROJECT),example) MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultRocketConfig + CONFIG ?= RocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomRocketTop + TOP ?= Top endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip)