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Merge remote-tracking branch 'origin/main' into clusters

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This commit is contained in:
Jerry Zhao
2023-12-15 15:53:35 -08:00
parent c5921ddef2 f882280290
commit e7f10348b0
80 changed files with 3722 additions and 2870 deletions
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6
fpga/Makefile
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@@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
FPGA_BRAND ?= xilinx
endif
ifeq ($(SUB_PROJECT),arty)
ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
MODEL ?= ArtyFPGATestHarness
VLOG_MODEL ?= ArtyFPGATestHarness
MODEL ?= Arty35THarness
VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty

8
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
import chipyard.iobinders._
class WithArtyDebugResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: DebugResetPort) => {
case (th: Arty35THarness, port: DebugResetPort) => {
th.dut_ndreset := port.io // Debug module reset
}
})
class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGResetPort) => {
case (th: Arty35THarness, port: JTAGResetPort) => {
port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
}
})
class WithArtyJTAGHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGPort) => {
case (th: Arty35THarness, port: JTAGPort) => {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := port.io.TDO
jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
})
class WithArtyUARTHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: UARTPort) => {
case (th: Arty35THarness, port: UARTPort) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_rxd_out, port.io.txd)
port.io.rxd := IOBUF(th.uart_txd_in)

2
fpga/src/main/scala/arty/IOBinders.scala
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@@ -18,6 +18,6 @@ class WithDebugResetPassthrough extends ComposeIOBinder({
val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
sjtag.reset := io_sjtag_reset
(Seq(DebugResetPort(io_ndreset), JTAGResetPort(io_sjtag_reset)), Nil)
(Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
}
})

3
fpga/src/main/scala/arty/TestHarness.scala
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@@ -9,9 +9,8 @@ import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{HasHarnessInstantiators}
import chipyard.iobinders.{HasIOBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ~ck_rst

38
fpga/src/main/scala/arty100t/Configs.scala
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@@ -21,18 +21,19 @@ class WithNoDesignKey extends Config((site, here, up) => {
case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
})
class WithArty100TTweaks extends Config(
class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
new chipyard.config.WithFrontBusFrequency(freqMHz) ++
new chipyard.config.WithSystemBusFrequency(freqMHz) ++
new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
new chipyard.config.WithControlBusFrequency(freqMHz) ++
new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
@@ -46,23 +47,14 @@ class RocketArty100TConfig extends Config(
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.RocketConfig)
class UART230400RocketArty100TConfig extends Config(
new WithArty100TUARTTSI(uartBaudRate = 230400) ++
new RocketArty100TConfig)
class UART460800RocketArty100TConfig extends Config(
new WithArty100TUARTTSI(uartBaudRate = 460800) ++
new RocketArty100TConfig)
class UART921600RocketArty100TConfig extends Config(
new WithArty100TUARTTSI(uartBaudRate = 921600) ++
new RocketArty100TConfig)
class NoCoresArty100TConfig extends Config(
new WithArty100TTweaks ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.NoCoresConfig)
// This will fail to close timing above 50 MHz
class BringupArty100TConfig extends Config(
new WithArty100TSerialTLToGPIO ++
new WithArty100TTweaks(freqMHz = 50) ++
new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new chipyard.ChipBringupHostConfig)

1
fpga/src/main/scala/arty100t/Harness.scala
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@@ -17,7 +17,6 @@ import sifive.blocks.devices.uart._
import chipyard._
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
def dp = designParameters

50
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -1,6 +1,7 @@
package chipyard.fpga.arty100t
import chisel3._
import chisel3.experimental.{DataMirror, Direction}
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
@@ -11,16 +12,17 @@ import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import chipyard._
import chipyard.harness._
import chipyard.iobinders._
import testchipip._
class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
ath.io_uart_bb.bundle <> port.io.uart
@@ -41,3 +43,43 @@ class WithArty100TDDRTL extends HarnessBinder({
ddrClientBundle <> port.io
}
})
// Uses PMOD JA/JB
class WithArty100TSerialTLToGPIO extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
harnessIO <> port.io
val clkIO = IOPin(harnessIO.clock)
val packagePinsWithPackageIOs = Seq(
("G13", clkIO),
("B11", IOPin(harnessIO.bits.out.valid)),
("A11", IOPin(harnessIO.bits.out.ready)),
("D12", IOPin(harnessIO.bits.in.valid)),
("D13", IOPin(harnessIO.bits.in.ready)),
("B18", IOPin(harnessIO.bits.out.bits, 0)),
("A18", IOPin(harnessIO.bits.out.bits, 1)),
("K16", IOPin(harnessIO.bits.out.bits, 2)),
("E15", IOPin(harnessIO.bits.out.bits, 3)),
("E16", IOPin(harnessIO.bits.in.bits, 0)),
("D15", IOPin(harnessIO.bits.in.bits, 1)),
("C15", IOPin(harnessIO.bits.in.bits, 2)),
("J17", IOPin(harnessIO.bits.in.bits, 3))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addPackagePin(io, pin)
artyTh.xdc.addIOStandard(io, "LVCMOS33")
}}
// Don't add IOB to the clock, if its an input
if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
}
artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
artyTh.sdc.addGroup(pins = Seq(clkIO))
artyTh.xdc.clockDedicatedRouteFalse(clkIO)
}
})

1
fpga/src/main/scala/nexysvideo/Harness.scala
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@@ -16,7 +16,6 @@ import sifive.blocks.devices.uart._
import chipyard._
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class NexysVideoHarness(override implicit val p: Parameters) extends NexysVideoShell {
def dp = designParameters

1
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -19,7 +19,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>

1
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {

4
fpga/src/main/scala/vcu118/bringup/IOBinders.scala
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@@ -13,7 +13,7 @@ import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
case class TSIHostWidgetPort(val io: TSIHostWidgetIO)
case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
extends Port[TSIHostWidgetIO]
class WithTSITLIOPassthrough extends OverrideIOBinder({
@@ -25,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
require(system.tsiSerial.size == 1)
val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
io_tsi_serial_pins_temp <> system.tsiSerial.head
(Seq(TLMemPort(io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(io_tsi_serial_pins_temp)), Nil)
(Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
}
})