diff --git a/generators/boom b/generators/boom
index 65b0d39b..9459af0c 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 65b0d39b35bb5dbb3deba826979c5145846648ae
+Subproject commit 9459af0c1f6847f8411622dac770ac78fe10847c
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index 7778deb6..6f211d8b 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -111,7 +111,7 @@ class SpikeTile(
     this(params, crossing.crossingType, lookup, p)
 
   // Required TileLink nodes
-  val intOutwardNode = Some(IntIdentityNode())
+  val intOutwardNode = None
   val masterNode = visibilityNode
   val slaveNode = TLIdentityNode()
 
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 54be0f8a..76b17273 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -117,7 +117,7 @@ class MyTile(
     this(params, crossing.crossingType, lookup, p)
 
   // Require TileLink nodes
-  val intOutwardNode = Some(IntIdentityNode())
+  val intOutwardNode = None
   val masterNode = visibilityNode
   val slaveNode = TLIdentityNode()
 
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 7fdc2a37..b94c1e3c 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -459,7 +459,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
       val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
       trace <> t
       val p = GetSystemParameters(system)
-      val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
+      val chipyardSystem = system.asInstanceOf[ChipyardSystem]
       val tiles = chipyardSystem.totalTiles.values
       val cfg = SpikeCosimConfig(
         isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
diff --git a/generators/cva6 b/generators/cva6
index 942d5aef..9d1c1068 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 942d5aef13ab82ce12adfd5346b2a2716832d69d
+Subproject commit 9d1c106834824ddb8052b7f60574b2b544b40395
diff --git a/generators/ibex b/generators/ibex
index b52a2d72..c2174aba 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit b52a2d721993d7b38982a0fa62b696798ac4dd9a
+Subproject commit c2174aba4fb304c7565c248f2a673f7151be896b
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index ebb45b94..bbfc3c35 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit ebb45b9439a19e2710ce0f2ee6e9ae2a192cbddf
+Subproject commit bbfc3c35100329386314c49b62b49a7f42f65e87
diff --git a/generators/shuttle b/generators/shuttle
index 924d269d..fd325d43 160000
--- a/generators/shuttle
+++ b/generators/shuttle
@@ -1 +1 @@
-Subproject commit 924d269d1ef81adfeb263a3d898c82105f7d50ed
+Subproject commit fd325d43a162378dc1984e87297e6d710167db79