[skip ci] remove need to set site_packages_dir

docs/VLSI/Advanced-Usage.rst

@@ -5,16 +5,12 @@ Advanced Usage
 
 Hammer Development
 ------------------
-If you need to develop Hammer within Chipyard, you will not use the ``hammer-vlsi`` package as installed by conda.
-
-First, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
+If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
 
 .. code-block:: shell
     
     pip install -e <path/to/hammer>
 
-Finally, you will need to override the ``site_packages_dir`` variable in ``vlsi/Makefile`` to point to the abspath of your Hammer repository.
-
 Alternative RTL Flows
 ---------------------
 The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).

vlsi/Makefile

@@ -8,7 +8,6 @@
 base_dir=$(abspath ..)
 vlsi_dir=$(abspath .)
 sim_dir=$(abspath .)
-site_packages_dir?=$(shell python3 -c "import site; print(site.getsitepackages()[0])")
 
 #########################################################################################
 # include shared variables
@@ -22,7 +21,8 @@ include $(base_dir)/variables.mk
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
 tech_name          ?= asap7
 tech_dir           ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
-                        $(site_packages_dir)/hammer/technology/$(tech_name), \
+                        $(shell python3 -c "import os, hammer.technology.$(tech_name);\
+						print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\
                         $(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/$(tech_name))
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
 SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json

vlsi/tutorial.mk

@@ -34,5 +34,5 @@ ifeq ($(tutorial),sky130-openroad)
     INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
     VLSI_OBJ_DIR      ?= build-sky130-openroad
     # This prevents multidimensional arrays (unsupported by Yosys) at the expense of elaboration time.
-    #ENABLE_CUSTOM_FIRRTL_PASS = 1
+    ENABLE_CUSTOM_FIRRTL_PASS = 1
 endif