From ebfe3103a45d2b7b4e62609baa083fb4a20647a7 Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Tue, 29 Sep 2020 17:33:49 -0700
Subject: [PATCH] [clocks] IdealizedPll -> DividerOnlyClockGenerator

---
 generators/chipyard/src/main/scala/Clocks.scala  | 12 ++++++------
 ...PLL.scala => DividerOnlyClockGenerator.scala} | 16 ++++++++--------
 2 files changed, 14 insertions(+), 14 deletions(-)
 rename generators/chipyard/src/main/scala/clocking/{IdealizedPLL.scala => DividerOnlyClockGenerator.scala} (87%)

diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index b54d5c42..554e9905 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider}
 
 import barstools.iocell.chisel._
 
-import chipyard.clocking.{IdealizedPLL, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
+import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
 
 /**
   * Chipyard provides three baseline, top-level reset schemes, set using the
@@ -79,12 +79,12 @@ object GenerateReset {
 }
 
 
-case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.idealizedPLL)
-/**
+case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.dividerOnlyClockGenerator)
+/*
   * This is a Seq of assignment functions, that accept a clock name and return an optional frequency.
   * Functions that appear later in this seq have higher precedence that earlier ones.
   * If no function returns a non-empty value, the value specified in
-  * [[DefaultClockFrequencyKey]] will be used -- DFU.
+  * [[DefaultClockFrequencyKey]] will be used.
   */
 case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty)
 case object DefaultClockFrequencyKey extends Field[Double]()
@@ -100,7 +100,7 @@ class ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((si
 })
 
 object ClockingSchemeGenerators {
-  val idealizedPLL: ChipTop => Unit = { chiptop =>
+  val dividerOnlyClockGenerator: ChipTop => Unit = { chiptop =>
     implicit val p = chiptop.p
 
     // Requires existence of undriven asyncClockGroups in subsystem
@@ -116,7 +116,7 @@ object ClockingSchemeGenerators {
     val referenceClockSource =  ClockSourceNode(Seq(ClockSourceParameters()))
     (aggregator
       := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
-      := IdealizedPLL()
+      := DividerOnlyClockGenerator()
       := referenceClockSource)
 
 
diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
similarity index 87%
rename from generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
rename to generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
index 8dfc7908..4355fc71 100644
--- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
+++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -26,12 +26,12 @@ object FrequencyUtils {
   }
 }
 
-class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters]) {
+class SimplePllConfiguration(name: String, val sinks: Seq[ClockSinkParameters]) {
   val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz
   val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*)
 
   private val preamble = s"""
-    |${pllName} Frequency Summary
+    |${name} Frequency Summary
     |  Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin
   private val outputSummaries = sinkDividerMap.map { case (sink, division) =>
       val requested = sink.take.get.freqMHz
@@ -40,11 +40,11 @@ class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters
     }
 
    val summaryString =  preamble + outputSummaries.mkString("\n")
-   ElaborationArtefacts.add(s"${pllName}.freq-summary", summaryString)
+   ElaborationArtefacts.add(s"${name}.freq-summary", summaryString)
    println(summaryString)
 }
 
-case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
+case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName)
   extends MixedNexusNode(ClockImp, ClockGroupImp)(
     dFn = { _ => ClockGroupSourceParameters() },
     uFn = { u =>
@@ -64,8 +64,8 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
   * frequency.
   */
 
-class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
-  val node = IdealizedPLLNode(pllName)
+class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
+  val node = DividerOnlyClockGeneratorNode(pllName)
 
   lazy val module = new LazyRawModuleImp(this) {
     require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator")
@@ -92,6 +92,6 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex
   }
 }
 
-object IdealizedPLL {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new IdealizedPLL(valName.name)).node
+object DividerOnlyClockGenerator {
+  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new DividerOnlyClockGenerator(valName.name)).node
 }