diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 3581ae3d..a8c54dc6 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -13,6 +13,7 @@ import sifive.blocks.devices.pinctrl._
 import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
 
 import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
+import chipyard.iobinders.JTAGChipIO
 
 class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
   (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
@@ -31,11 +32,18 @@ class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
 class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
   (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
     ports.map {
-      case j: JTAGIO =>
+      case j: JTAGChipIO =>
         withClockAndReset(th.buildtopClock, th.hReset) {
+          val jtag_wire = Wire(new JTAGIO)
+          jtag_wire.TDO.data := j.TDO
+          jtag_wire.TDO.driven := true.B
+          j.TCK := jtag_wire.TCK
+          j.TMS := jtag_wire.TMS
+          j.TDI := jtag_wire.TDI
+
           val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
 
-          JTAGPinsFromPort(io_jtag, j)
+          JTAGPinsFromPort(io_jtag, jtag_wire)
 
           io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
 
diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
index b87659f4..da497a54 100644
--- a/generators/chipyard/src/main/scala/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -22,7 +22,7 @@ import barstools.iocell.chisel._
 import testchipip._
 
 import chipyard.{HasHarnessSignalReferences, HarnessClockInstantiatorKey}
-import chipyard.iobinders.GetSystemParameters
+import chipyard.iobinders.{GetSystemParameters, JTAGChipIO}
 
 import tracegen.{TraceGenSystemModuleImp}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
@@ -245,10 +245,16 @@ class WithSimDebug extends OverrideHarnessBinder({
         val dtm_success = WireInit(false.B)
         when (dtm_success) { th.success := true.B }
         val dtm = Module(new SimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success)
-      case j: JTAGIO =>
+      case j: JTAGChipIO =>
         val dtm_success = WireInit(false.B)
         when (dtm_success) { th.success := true.B }
-        val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success)
+        val jtag_wire = Wire(new JTAGIO)
+        jtag_wire.TDO.data := j.TDO
+        jtag_wire.TDO.driven := true.B
+        j.TCK := jtag_wire.TCK
+        j.TMS := jtag_wire.TMS
+        j.TDI := jtag_wire.TDI
+        val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success)
     }
   }
 })
@@ -256,11 +262,10 @@ class WithSimDebug extends OverrideHarnessBinder({
 class WithTiedOffDebug extends OverrideHarnessBinder({
   (system: HasPeripheryDebug, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
     ports.map {
-      case j: JTAGIO =>
+      case j: JTAGChipIO =>
         j.TCK := true.B.asClock
         j.TMS := true.B
         j.TDI := true.B
-        j.TRSTn.foreach { r => r := true.B }
       case d: ClockedDMIIO =>
         d.dmi.req.valid := false.B
         d.dmi.req.bits  := DontCare
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index c55d86e0..5d153834 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -199,6 +199,13 @@ class WithExtInterruptIOCells extends OverrideIOBinder({
   }
 })
 
+// Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip
+class JTAGChipIO extends Bundle {
+  val TCK = Input(Clock())
+  val TMS = Input(Bool())
+  val TDI = Input(Bool())
+  val TDO = Output(Bool())
+}
 
 class WithDebugIOCells extends OverrideLazyIOBinder({
   (system: HasPeripheryDebug) => {
@@ -238,7 +245,12 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
         }
 
         val jtagTuple = debug.systemjtag.map { j =>
-          IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = true)
+          val jtag_wire = Wire(new JTAGChipIO)
+          j.jtag.TCK := jtag_wire.TCK
+          j.jtag.TMS := jtag_wire.TMS
+          j.jtag.TDI := jtag_wire.TDI
+          jtag_wire.TDO := j.jtag.TDO.data
+          IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
         }
 
         val apbTuple = debug.apb.map { a =>