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Merge pull request #1576 from ucb-bar/rocket-async

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Fix asyncqueue depth in ChipLikeRocketConfig
This commit is contained in:
Jerry Zhao
2023-08-16 10:09:57 -07:00
committed by GitHub
parent c9ed05057b 453903dbc7
commit ed96a11a26
1 changed files with 1 additions and 1 deletions
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generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config(
//================================== //==================================
// Set up tiles // Set up tiles
//================================== //==================================
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++ // Add async crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile
//================================== //==================================