From f1fdab5bd337cc72563100296d54648393049882 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 23 Nov 2020 16:58:34 -0800 Subject: [PATCH] Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem --- fpga/src/main/scala/vcu118/Configs.scala | 7 +------ generators/chipyard/src/main/scala/ConfigFragments.scala | 5 +++++ generators/chipyard/src/main/scala/System.scala | 4 ++++ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 5bd21245..8b17aa98 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -39,11 +39,6 @@ class WithSystemModifications extends Config((site, here, up) => { case SerialTLKey => None // remove serialized tl port }) -class WithTLBackingMemory extends Config((site, here, up) => { - case ExtMem => None // disable AXI backing memory - case ExtTLMem => up(ExtMem, site) // enable TL backing memory -}) - // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( new WithUART ++ @@ -53,7 +48,7 @@ class WithVCU118Tweaks extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithTLBackingMemory ++ // use TL backing memory + new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 4bc0b9a2..749c75bb 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -181,6 +181,11 @@ class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusW case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) }) +class WithTLBackingMemory extends Config((site, here, up) => { + case ExtMem => None // disable AXI backing memory + case ExtTLMem => up(ExtMem, site) // enable TL backing memory +}) + class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 4ab0da3e..31bedae7 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -51,6 +51,10 @@ case object ExtTLMem extends Field[Option[MemoryPortParams]](None) /** Adds a port to the system intended to master an TL DRAM controller. */ trait CanHaveMasterTLMemPort { this: BaseSubsystem => + + require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty), + "Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.") + private val memPortParamsOpt = p(ExtTLMem) private val portName = "tl_mem" private val device = new MemoryDevice