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update mem docs | add l1 scratchpad config

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abejgonzalez
2020-05-25 14:29:07 -07:00
parent c2c9bc83de
commit f24fd2a113
2 changed files with 37 additions and 7 deletions
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15
docs/Customization/Memory-Hierarchy.rst
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@@ -31,8 +31,8 @@ Note that these configurations fully remove the L2 cache and mbus.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
:language: scala
:start-after: DOC include start: scratchpadrocket
:end-before: DOC include end: scratchpadrocket
:start-after: DOC include start: l1scratchpadrocket
:end-before: DOC include end: l1scratchpadrocket
This configuration fully removes the L2 cache and memory bus by setting the
@@ -94,11 +94,20 @@ number of DRAM channels is restricted to powers of two.
new freechips.rocketchip.subsystem.WithNMemoryChannels(2)
In VCS and Verilator simulation, the DRAM is simulated using the
``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each
memory channel.
Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
and remove the off-chip link. This is done by adding a fragment like
``testchipip.WithBackingScratchpad`` to your configuration and removing the
memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
:language: scala
:start-after: DOC include start: mbusscratchpadrocket
:end-before: DOC include end: mbusscratchpadrocket
If you want a more realistic memory simulation, you can use FireSim, which
can simulate the timing of DDR3 controllers. More documentation on FireSim
memory models is available in the `FireSim docs <https://docs.fires.im/en/latest/>`_.