wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

update mem docs | add l1 scratchpad config

Browse Source
This commit is contained in:
abejgonzalez
2020-05-25 14:29:07 -07:00
parent c2c9bc83de
commit f24fd2a113
2 changed files with 37 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
docs/Customization/Memory-Hierarchy.rst
View File

@@ -31,8 +31,8 @@ Note that these configurations fully remove the L2 cache and mbus.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
:language: scala :language: scala
:start-after: DOC include start: scratchpadrocket :start-after: DOC include start: l1scratchpadrocket
:end-before: DOC include end: scratchpadrocket :end-before: DOC include end: l1scratchpadrocket
This configuration fully removes the L2 cache and memory bus by setting the This configuration fully removes the L2 cache and memory bus by setting the
@@ -94,11 +94,20 @@ number of DRAM channels is restricted to powers of two.
new freechips.rocketchip.subsystem.WithNMemoryChannels(2) new freechips.rocketchip.subsystem.WithNMemoryChannels(2)
In VCS and Verilator simulation, the DRAM is simulated using the In VCS and Verilator simulation, the DRAM is simulated using the
``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each
memory channel. memory channel.
Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
and remove the off-chip link. This is done by adding a fragment like
``testchipip.WithBackingScratchpad`` to your configuration and removing the
memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
:language: scala
:start-after: DOC include start: mbusscratchpadrocket
:end-before: DOC include end: mbusscratchpadrocket
If you want a more realistic memory simulation, you can use FireSim, which If you want a more realistic memory simulation, you can use FireSim, which
can simulate the timing of DDR3 controllers. More documentation on FireSim can simulate the timing of DDR3 controllers. More documentation on FireSim
memory models is available in the `FireSim docs <https://docs.fires.im/en/latest/>`_. memory models is available in the `FireSim docs <https://docs.fires.im/en/latest/>`_.

29
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -384,14 +384,35 @@ class LoopbackNICRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
// DOC include start: scratchpadrocket // DOC include start: l1scratchpadrocket
class ScratchpadRocketConfig extends Config( class L1ScratchpadSmallRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++ new testchipip.WithTSI ++
new testchipip.WithBackingScratchpad ++ // add backing scratchpad new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: l1scratchpadrocket
// DOC include start: mbusscratchpadrocket
class MbusScratchpadRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++ new chipyard.config.WithL2TLBs(1024) ++
@@ -403,7 +424,7 @@ class ScratchpadRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
// DOC include end: scratchpadrocket // DOC include end: mbusscratchpadrocket
// DOC include start: RingSystemBusRocket // DOC include start: RingSystemBusRocket
class RingSystemBusRocketConfig extends Config( class RingSystemBusRocketConfig extends Config(