diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 86c28f23..e8a30b0c 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,10 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +include $(base_dir)/vcs.mk .PHONY: default debug default: $(sim) diff --git a/vcs.mk b/vcs.mk new file mode 100644 index 00000000..c0450da5 --- /dev/null +++ b/vcs.mk @@ -0,0 +1,35 @@ +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off + +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd + +VCS_CC_OPTS = \ + -CC "-I$(VCS_HOME)/include" \ + -CC "-I$(RISCV)/include" \ + -CC "-std=c++11" + +VCS_NONCC_OPTS = \ + $(RISCV)/lib/libfesvr.a \ + +lint=all,noVCDE,noONGS,noUI \ + -error=PCWM-L \ + -timescale=1ns/10ps \ + -quiet \ + -q \ + +rad \ + +v2k \ + +vcs+lic+wait \ + +vc+list \ + -f $(sim_common_files) \ + -sverilog \ + +incdir+$(build_dir) \ + $(sim_vsrcs) \ + +libext+.v + +VCS_DEFINE_OPTS = \ + +define+CLOCK_PERIOD=1.0 \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN diff --git a/vlsi/Makefile b/vlsi/Makefile index a41368c5..800411bd 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -87,11 +87,123 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator cd $(vlsi_dir) && cp output.json $@ +######################################################################################### +# simulation input configuration +######################################################################################### +include $(base_dir)/vcs.mk +SIM_CONF = $(OBJ_DIR)/sim-inputs.yml +SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml + +$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " level: 'gl'" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options: [" >> $@ + echo " '$(RISCV)/lib/libfesvr.a'," >> $@ + echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ + echo " '-error=PCWM-L'," >> $@ + echo " '-quiet'," >> $@ + echo " '-q'," >> $@ + echo " '+rad'," >> $@ + echo " '+v2k'," >> $@ + echo " '+vcs+lic+wait'," >> $@ + echo " '+vc+list'," >> $@ + echo " '-f $(sim_common_files)'," >> $@ + echo " '-sverilog']" >> $@ + echo " options_meta: 'append'" >> $@ + echo " defines: [" >> $@ + echo " 'CLOCK_PERIOD=1.0'," >> $@ + echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ + echo " 'STOP_COND=!$(TB).reset'," >> $@ + echo " 'RANDOMIZE_MEM_INIT'," >> $@ + echo " 'RANDOMIZE_REG_INIT'," >> $@ + echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ + echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " compiler_opts: [" >> $@ + echo " '-I$(RISCV)/include'," >> $@ + echo " '-std=c++11']" >> $@ + echo " compiler_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags: [" >> $@ + echo " '+max-cycles=$(timeout_cycles)'," >> $@ + for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " ]" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + +$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " level: 'gl'" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options: [" >> $@ + echo " '$(RISCV)/lib/libfesvr.a'," >> $@ + echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ + echo " '-error=PCWM-L'," >> $@ + echo " '-quiet'," >> $@ + echo " '-q'," >> $@ + echo " '+rad'," >> $@ + echo " '+v2k'," >> $@ + echo " '+vcs+lic+wait'," >> $@ + echo " '+vc+list'," >> $@ + echo " '-f $(sim_common_files)'," >> $@ + echo " '-sverilog'," >> $@ + echo " '-debug_pp']" >> $@ + echo " options_meta: 'append'" >> $@ + echo " defines: [" >> $@ + echo " 'DEBUG'," >> $@ + echo " 'CLOCK_PERIOD=1.0'," >> $@ + echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ + echo " 'STOP_COND=!$(TB).reset'," >> $@ + echo " 'RANDOMIZE_MEM_INIT'," >> $@ + echo " 'RANDOMIZE_REG_INIT'," >> $@ + echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ + echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " compiler_opts: [" >> $@ + echo " '-I$(RISCV)/include'," >> $@ + echo " '-std=c++11']" >> $@ + echo " compiler_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags: [" >> $@ + echo " '+max-cycles=$(timeout_cycles)'," >> $@ + for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + echo " tb_dut: 'testHarness.top'" >> $@ + echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + + #echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@ + +$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "power.inputs:" > $@ + +sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF) + ######################################################################################### # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) +GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF) ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif