From f4739be632806388ee9adf41a67186f495db3fed Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 14 May 2023 21:49:04 -0700 Subject: [PATCH] Update multi-chip API for harnesses --- fpga/src/main/scala/arty100t/Harness.scala | 2 -- fpga/src/main/scala/vc707/TestHarness.scala | 2 -- fpga/src/main/scala/vcu118/TestHarness.scala | 2 -- .../harness/HasHarnessInstantiators.scala | 18 +++++++++++------- .../src/main/scala/harness/TestHarness.scala | 2 ++ .../firechip/src/main/scala/FireSim.scala | 2 ++ 6 files changed, 15 insertions(+), 13 deletions(-) diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 64b4b28d..94ba6b45 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -22,8 +22,6 @@ import chipyard.iobinders.{HasIOBinders} class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell { def dp = designParameters - require(dp(MultiChipNChips) == 0, "Arty100T harness does not support multi-chip") - val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head val harnessSysPLL = dp(PLLFactoryKey) val harnessSysPLLNode = harnessSysPLL() diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index b78b0fe3..1293d26a 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -88,8 +88,6 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She } class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators { - require (p(MultiChipNChips) == 0) - val vc707Outer = _outer val reset = IO(Input(Bool())) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index cc87c4ea..07a5f8b4 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -91,8 +91,6 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S } class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators { - require(p(MultiChipNChips) == 0) - val vcu118Outer = _outer val reset = IO(Input(Bool())) diff --git a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala index a66db4af..b5c7e2ce 100644 --- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala +++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala @@ -18,7 +18,7 @@ import chipyard.{ChipTop} // Chipyard Test Harness // ------------------------------- -case object MultiChipNChips extends Field[Int](0) // 0 means ignore MultiChipParams +case object MultiChipNChips extends Field[Option[Int]](None) // None means ignore MultiChipParams case class MultiChipParameters(chipId: Int) extends Field[Parameters] case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator]() @@ -27,12 +27,12 @@ case object MultiChipIdx extends Field[Int](0) class WithMultiChip(id: Int, p: Parameters) extends Config((site, here, up) => { case MultiChipParameters(`id`) => p - case MultiChipNChips => up(MultiChipNChips) max (id + 1) + case MultiChipNChips => Some(up(MultiChipNChips).getOrElse(0) max (id + 1)) }) class WithHomogeneousMultiChip(n: Int, p: Parameters, idStart: Int = 0) extends Config((site, here, up) => { case MultiChipParameters(id) => if (id >= idStart && id < idStart + n) p else up(MultiChipParameters(id)) - case MultiChipNChips => up(MultiChipNChips) max (idStart + n) + case MultiChipNChips => Some(up(MultiChipNChips).getOrElse(0) max (idStart + n)) }) class WithHarnessBinderClockFreqMHz(freqMHz: Double) extends Config((site, here, up) => { @@ -61,17 +61,21 @@ trait HasHarnessInstantiators { // This can be accessed to get new clocks from the harness val harnessClockInstantiator = p(HarnessClockInstantiatorKey)() - private val chipParameters = if (p(MultiChipNChips) == 0) { - Seq(p) - } else { - (0 until p(MultiChipNChips)).map { i => p(MultiChipParameters(i)).alterPartial { + val supportsMultiChip: Boolean = false + + private val chipParameters = p(MultiChipNChips) match { + case Some(n) => (0 until n).map { i => p(MultiChipParameters(i)).alterPartial { case TargetDirKey => p(TargetDirKey) // hacky fix case MultiChipIdx => i }} + case None => Seq(p) } // This shold be called last to build the ChipTops def instantiateChipTops(): Seq[LazyModule] = { + require(p(MultiChipNChips).isEmpty || supportsMultiChip, + s"Selected Harness does not support multi-chip") + val lazyDuts = chipParameters.zipWithIndex.map { case (q,i) => LazyModule(q(BuildTop)(q)).suggestName(s"chiptop$i") } diff --git a/generators/chipyard/src/main/scala/harness/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala index 2f75ac8d..e1f659b4 100644 --- a/generators/chipyard/src/main/scala/harness/TestHarness.scala +++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala @@ -24,6 +24,8 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessInst val success = WireInit(false.B) io.success := success + override val supportsMultiChip = true + // By default, the chipyard makefile sets the TestHarness implicit clock to be 1GHz // This clock shouldn't be used by this TestHarness however, as most users // will use the AbsoluteFreqHarnessClockInstantiator, which generates clocks diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index a2f24dcb..be016e6a 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -77,6 +77,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta def referenceReset = resetBridge.io.reset def success = { require(false, "success should not be used in Firesim"); false.B } + override val supportsMultiChip = true + instantiateChipTops() // Ensures FireSim-synthesized assertions and instrumentation is disabled