diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 103fea91..23f3f56a 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -38,7 +38,7 @@ We also see this class define several ``ElaborationArtefacts``, files emitted af Subsystem ^^^^^^^^^^^^^^^^^^^^^^^^^ -Looking in `generators/chipyard/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` +Looking in `generators/chipyard/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that defines and instantiates BOOM or Rocket tiles, depending on the parameters specified. We also connect some basic IOs for each tile here, specifically the hartids and the reset vector. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 1b9a8512..713bf772 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -47,6 +47,9 @@ Accelerators System Components: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +**constellation** + A generator for network-on-chip (NoC) interconnects. + **icenet** A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. diff --git a/docs/Customization/NoC-SoCs.rst b/docs/Customization/NoC-SoCs.rst new file mode 100644 index 00000000..b96556fd --- /dev/null +++ b/docs/Customization/NoC-SoCs.rst @@ -0,0 +1,34 @@ +SoCs with NoC-based Interconnects +================================== + +The primary way to integrate a network-on-chip into a Chipyard SoC is to map one of the standard TileLink crossbar-based buses (System Bus, Memory Bus, Control Bus, etc.) to a Constellation-generated NoC. + +The interconnect can be mapped as a "private" interconnect for the TileLink bus, in which case a dedicated interconnect to carry the bus traffic will be generated. +Alternatively, the interconnect can be mapped to a shared global interconnect, in which case multiple TileLink buses can be transported over a single shared interconnect. + +Private Interconnects +--------------------- +An example of integrating dedicated private interconnects for the System Bus, Memory Bus, and Control Bus can be seen in the ``MultiNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala `__. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala + :language: scala + :start-after: DOC include start: MultiNoCConfig + :end-before: DOC include end: MultiNoCConfig + +Note that for each bus (``Sbus`` / ``Mbus`` / ``Cbus``), the configuration fragment provides both a parameterization of the private NoC, as well as a mapping between TileLink agents and physical NoC nodes. + +For more information on how to construct the NoC parameters, see the `Constellation documentation `__. + + +Shared Global Interconnect +--------------------------- +An example of integrating a single global interconnect that supports transporting multiple TileLink buses can be seen in the ``SharedNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala `__. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala + :language: scala + :start-after: DOC include start: SharedNoCConfig + :end-before: DOC include end: SharedNoCConfig + +Note that for each bus, the configuration fragment provides only the mapping between TileLink agents and physical NoC nodes, while a separate fragement provides the configuration for the global interconnect. + +For more information on how to construct the NoC parameters, see the `Constellation documentation `__. diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index a7b571b6..8e268059 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -3,7 +3,9 @@ Customization These guides will walk you through customization of your system-on-chip: -- Contructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system. +- Constructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system. + +- Constructing SoCs with a NoC (network-on-chip) based interconnect using Constellation - How to include your custom Chisel sources in the Chipyard build system @@ -36,6 +38,7 @@ We recommend reading all these pages in order. Hit next to get started! :caption: Customization: Heterogeneous-SoCs + NoC-SoCs Custom-Chisel Custom-Core RoCC-or-MMIO diff --git a/docs/Generators/Constellation.rst b/docs/Generators/Constellation.rst new file mode 100644 index 00000000..435544a9 --- /dev/null +++ b/docs/Generators/Constellation.rst @@ -0,0 +1,17 @@ +Constellation +======================== + +.. image:: ../_static/images/bigsoc.svg + +`Constellation `__ is a Chisel NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures. + + - Constellation generates **packet-switched wormhole-routed networks with virtual networks and credit-based flow control** + - Constellation supports **arbitrary directed graph network topologies**, including **irregular** and **hierarchical** network topologies + - Constellation includes a **routing algorithm verifier and routing-table compiler**, which can verify and generate deadlock-free routing tables for arbitrary topologies + - Constellation is a **protocol-independent transport layer**, yet is capable of compliant deadlock-free transport of protocols like **AXI-4** and **TileLink** + - Constellation supports drop-in **integration in Chipyard/Rocketchip SoCs** + - Constellation is **rigorously tested**, with almost 100 different tests across as many network configurations + +Constellation is fully integrated into Chipyard, and can be used to generate almost any interconnect in a Chipyard/Rocketchip-based SoC. + +For documentation on Constellation, see its `documentation pages `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 27e18e77..b491bae6 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -21,6 +21,7 @@ so changes to the generators themselves will automatically be used when building Rocket-Chip Rocket BOOM + Constellation Hwacha Gemmini IceNet diff --git a/docs/_static/images/bigsoc.svg b/docs/_static/images/bigsoc.svg new file mode 100644 index 00000000..fa81a893 --- /dev/null +++ b/docs/_static/images/bigsoc.svg @@ -0,0 +1,558 @@ + + + + + + + + + + + + + + + + + Canvas 18 + + Layer 2 + + + + + Big Core + + + + + + + L2 Bank + + + + + + + L2 Bank + + + + + + + Medium Core + + + + + + + Small Core + + + + + + + Small Core + + + + + + + Small Core + + + + + + + Small Core + + + + + + + ML Accelerator + + + + + + + Medium Core + + + + + + + Medium Core + + + + + + + DRAM Channel + + + + + + + DRAM Channel + + + + + + + DRAM Channel + + + + + + + DRAM Channel + + + + + + + ISP + + + + + + + I/O + + + + + + + RAM + + + + + + + DSP + + + + + + + Debug + + + + + + + JTAG + + + + + + + NIC + + + + + + + Small Core + + + + + + + Small Core + + + + + + + Small Core + + + + + + + Small Core + + + + + + + L2 Bank + + + + + + + L2 Bank + + + + + + + + + + + + + + + Big Core + + + + + + + I/O + + + + + Layer 3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 881da769..c5ad178a 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -60,7 +60,7 @@ import scala.collection.immutable.ListMap * | | | | | * |______________|______________|______________|______________| */ - +// DOC include start: MultiNoCConfig class MultiNoCConfig extends Config( new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( @@ -106,7 +106,7 @@ class MultiNoCConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ new chipyard.config.AbstractConfig ) - +// DOC include end: MultiNoCConfig /* * 10 - 11 - 12 - 13 - 14 @@ -147,6 +147,7 @@ class MultiNoCConfig extends Config( * DRAM 1 | MO | system[1] | 5 * extram | MO | serdesser | 9 */ +// DOC include start: SharedNoCConfig class SharedNoCConfig extends Config( new constellation.soc.WithGlobalNoC(GlobalNoCParams( NoCParams( @@ -184,3 +185,4 @@ class SharedNoCConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ new chipyard.config.AbstractConfig ) +// DOC include end: SharedNoCConfig