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Bump to pre-merge chipsalliance/rocket-chip#2764 to get it
going while picking up the chisel/firrtl bugfixes in 3/1.4.1+
This commit is contained in:
Tim Snyder
2020-12-18 17:56:01 +00:00
committed by Tim Snyder
parent 8836f84c79
commit f693972e12
4 changed files with 5 additions and 5 deletions
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4
build.sbt
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@@ -72,7 +72,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
// -- Rocket Chip --
// This needs to stay in sync with the chisel3 and firrtl git submodules
val chiselVersion = "3.4.0"
val chiselVersion = "3.4.1"
lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel")
lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion
lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies)
@@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies)
// keeping scalaVersion in sync with chisel3 to the minor version
lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full
val firrtlVersion = "1.4.+"
val firrtlVersion = "1.4.1"
lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl")
lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion
val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4")

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 577994e38e...a7b016e46e

2
tools/chisel3

Submodule tools/chisel3 updated: d379dca441...58d38f9620

2
tools/firrtl

Submodule tools/firrtl updated: 05d047a9be...7756f8f963