diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index eb7b4086..ea245fbc 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config}
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -15,6 +16,7 @@ class Sodor1StageConfig extends Config(
 class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -23,6 +25,7 @@ class Sodor2StageConfig extends Config(
 class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -31,6 +34,7 @@ class Sodor3StageConfig extends Config(
 class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -39,6 +43,7 @@ class Sodor3StageSinglePortConfig extends Config(
 class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -47,6 +52,7 @@ class Sodor5StageConfig extends Config(
 class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
diff --git a/generators/testchipip b/generators/testchipip
index bdca33ec..bd0ff2d0 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit bdca33ec1684e6e00df2f5c9aebc0b41fb593585
+Subproject commit bd0ff2d0c61023549304709ce0d377a837564295