diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index f2d77a5f..8f9ab029 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -193,19 +193,16 @@ class WithTLBackingMemory extends Config((site, here, up) => { case ExtTLMem => up(ExtMem, site) // enable TL backing memory }) -class WithOffchipBackingMemory extends Config((site, here, up) => { +class WithSerialTLBackingMemory extends Config((site, here, up) => { case ExtMem => None - case SerialTLKey => Some(SerialTLParams( + case SerialTLKey => up(SerialTLKey, site).map { k => k.copy( memParams = { val memPortParams = up(ExtMem, site).get - require(memPortParams.nMemoryChannels == 1) - memPortParams.master }, - width = 4, isMemoryDevice = true - )) + )} }) class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 95382f6e..54110ebe 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -139,25 +139,30 @@ class WithSimAXIMem extends OverrideHarnessBinder({ } }) -class WithOffchipNetwork(offchipFreqMHz: Double = 1000) extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[ClockedIO[SerialIO]]]) => { +class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[SerialAndPassthroughClockResetIO]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) - ports.map({ port => - val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset) - val success = SerialAdapter.connectSimSerial(offchipNetwork.module.io.tsi_ser, port.bits.clock, th.harnessReset.asBool) - when (success) { th.success := true.B } + p(SerialTLKey).map({ sVal => + require(sVal.axiDomainClockFreqMHz.isDefined) + val freqRequested = sVal.axiDomainClockFreqMHz.get - // connect SimAxiMem - (offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (off_port, edge) => - val memSize = p(SerialTLKey).get.memParams.size - val lineSize = p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, offchipFreqMHz.toInt*1000000, edge.bundle)).suggestName("simdram") - mem.io.axi <> off_port - // use the clk from the ClockAndResetIO - mem.io.clock := port.clock - mem.io.reset := port.reset - } + ports.map({ port => + val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(system.serdesser.get, port, th.harnessReset) + val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clocked_serial.clock, th.harnessReset.asBool) + when (success) { th.success := true.B } + + // connect SimDRAM from the AXI port coming from the harness multi clock axi ram + (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memAXI4Node.edges.in).map { case (axi_port, edge) => + val memSize = sVal.memParams.size + val lineSize = p(CacheBlockBytes) + val mem = Module(new SimDRAM(memSize, lineSize, (freqRequested.toInt)*1000000, edge.bundle)).suggestName("simdram") + mem.io.axi <> axi_port + // use the clk from the ClockAndResetIO + mem.io.clock := port.passthrough_clock_reset.clock + mem.io.reset := port.passthrough_clock_reset.reset + } + }) }) } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index eff75ae2..26189ec5 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -260,33 +260,35 @@ class WithSerialTLIOCells extends OverrideIOBinder({ }).getOrElse((Nil, Nil)) }) -class WithSerialTLAndOffchipClockPunchthrough(offchipFreqMHz: Double = 1000) extends OverrideLazyIOBinder({ - (system: CanHavePeripheryTLSerial) => { +class WithSerialTLAndPassthroughClockPunchthrough extends OverrideLazyIOBinder({ + (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s => implicit val p: Parameters = GetSystemParameters(system) - val serial_clked_tl = system.serial_tl val sys = system.asInstanceOf[BaseSubsystem] - val externalDRAMClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = offchipFreqMHz))))) - (externalDRAMClockSinkNode - := ClockGroup()(p, ValName("OffchipClocking")) + require(p(SerialTLKey).isDefined) + val sVal = p(SerialTLKey).get + + require(sVal.axiDomainClockFreqMHz.isDefined) + val freqRequested = sVal.axiDomainClockFreqMHz.get + + // request clock to pass along + val externalAXIDomainClkSinkNode = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = freqRequested))))) + (externalAXIDomainClkSinkNode + := ClockGroup()(p, ValName("axi_mem_clock_domain")) := sys.asyncClockGroupsNode) - def clockBundle = externalDRAMClockSinkNode.in.head._1 + def clockBundle = externalAXIDomainClkSinkNode.in.head._1 InModuleBody { // 1st clock+reset is for offchip, 2nd clock (attached to serial io is the serial clock) - val port: Option[ClockedAndResetIO[ClockedIO[SerialIO]]] = serial_clked_tl.map({ s_io => - val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[ClockedIO[SerialIO]](s_io))).suggestName(s"serial_tl_offchip_clk") - p.bits <> s_io - p.clock := clockBundle.clock - p.reset := clockBundle.reset - p - }) + val port = IO(new SerialAndPassthroughClockResetIO(sVal.width)).suggestName(s"serial_tl_passthrough_clk") + port.clocked_serial <> s + port.passthrough_clock_reset <> clockBundle // return the ports and no IO cells - (Seq(port.get), Nil) + (Seq(port), Nil) } - } + }).getOrElse(InModuleBody{(Nil, Nil)}).asInstanceOf[ModuleValue[IOBinderTuple]] }) class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({ diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 043bd45e..da84bd05 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -54,47 +54,3 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system - -class AbstractOffChipConfig extends Config( - // The HarnessBinders control generation of hardware in the TestHarness - new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present - new chipyard.harness.WithOffchipNetwork ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled - new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present - new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled - new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled - new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present - new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present - - // The IOBinders instantiate ChipTop IOs to match desired digital IOs - // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through - new chipyard.iobinders.WithAXI4MemPunchthrough ++ - new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ - new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ - new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ - new chipyard.iobinders.WithNICIOPunchthrough ++ - new chipyard.iobinders.WithSerialTLAndOffchipClockPunchthrough ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ - new chipyard.iobinders.WithGPIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ - new chipyard.iobinders.WithSPIIOCells ++ - new chipyard.iobinders.WithTraceIOPunchthrough ++ - new chipyard.iobinders.WithExtInterruptIOCells ++ - - new chipyard.config.WithOffchipBackingMemory ++ - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks - new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) - new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus - new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus - new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 4d93f8e9..11bf9c4f 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -214,37 +214,37 @@ class LBWIFRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz) -class DebugOffchipConfig extends Config( - new testchipip.WithSerialTLWidth(64) ++ - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus - new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast - new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq. - - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // everything default to 3.2GHz - new chipyard.config.WithPeripheryBusFrequency(3200) ++ - new chipyard.config.WithMemoryBusFrequency(3200) ++ - - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores - new chipyard.config.AbstractOffChipConfig) // new offchip network where AXI is in harness - -// have pbus=3.2GHz,/1, but others are different (fbus=/4, other=/2) -class DebugOffchip2Config extends Config( - new chipyard.config.WithCbusToPbusCrossingType(RationalCrossing(SlowToFast)) ++ - new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ - - new chipyard.config.WithSystemBusFrequencyAsDefault ++ - new chipyard.config.WithSystemBusFrequency(3200 / 2) ++ - - new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ - new chipyard.config.WithPeripheryBusFrequency(3200) ++ - new chipyard.config.WithMemoryBusFrequency(3200) ++ - - new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS - - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores - new chipyard.config.AbstractOffChipConfig) +//// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz) +//class DebugOffchipConfig extends Config( +// new testchipip.WithSerialTLWidth(64) ++ +// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus +// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast +// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq. +// +// new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // everything default to 3.2GHz +// new chipyard.config.WithPeripheryBusFrequency(3200) ++ +// new chipyard.config.WithMemoryBusFrequency(3200) ++ +// +// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores +// new chipyard.config.AbstractOffChipConfig) // new offchip network where AXI is in harness +// +//// have pbus=3.2GHz,/1, but others are different (fbus=/4, other=/2) +//class DebugOffchip2Config extends Config( +// new chipyard.config.WithCbusToPbusCrossingType(RationalCrossing(SlowToFast)) ++ +// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ +// +// new chipyard.config.WithSystemBusFrequencyAsDefault ++ +// new chipyard.config.WithSystemBusFrequency(3200 / 2) ++ +// +// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ +// new chipyard.config.WithPeripheryBusFrequency(3200) ++ +// new chipyard.config.WithMemoryBusFrequency(3200) ++ +// +// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast +// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS +// +// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores +// new chipyard.config.AbstractOffChipConfig) // fbus=/2, other=/1 class DebugOffchip3Config extends Config( @@ -257,8 +257,13 @@ class DebugOffchip3Config extends Config( new chipyard.config.WithFrontBusFrequency(4000 / 2) ++ - new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS + new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores - new chipyard.config.AbstractOffChipConfig) + new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled + new chipyard.iobinders.WithSerialTLAndPassthroughClockPunchthrough ++ // add new clock for axi domain over serdes and passthrough ios + //new testchipip.WithAXIDomainFreq(1000.0) ++ // set offchip axi domain clock freq (match FireSim DRAM) + new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory + + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 6f74b770..eb48cc47 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -103,29 +103,33 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({ } }) -class WithOffchipNetworkSerialAXIBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedAndResetIO[ClockedIO[SerialIO]]]) => { +class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ + (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[SerialAndPassthroughClockResetIO]]]) => { implicit val p = GetSystemParameters(system) - ports.map({ port => - val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset) - SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(SerialTLKey).map(v => MainMemoryConsts.globalName)) - p(SerialTLKey).map(v => require(v.isMemoryDevice)) + p(SerialTLKey).map({ sVal => + // require having memory over the serdes link + require(sVal.isMemoryDevice) - // connect SimAxiMem - (offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) => - val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, - axi4.ar.bits.addr.getWidth, - axi4.ar.bits.id.getWidth) - system match { - case s: BaseSubsystem => FASEDBridge(port.clock, axi4, port.reset.asBool, - CompleteConfig(p(firesim.configs.MemModelKey), - nastiKey, - Some(AXI4EdgeSummary(edge)), - Some(MainMemoryConsts.globalName))) - case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design") + ports.map({ port => + val offchipNetwork = SerialAdapter.connectHarnessMultiClockAXIRAM(system.serdesser.get, port, th.harnessReset) + SerialBridge(port.clocked_serial.clock, offchipNetwork.module.io.tsi_ser, MainMemoryConsts.globalName) + + // connect SimAxiMem + (offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) => + val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, + axi4.ar.bits.addr.getWidth, + axi4.ar.bits.id.getWidth) + system match { + case s: BaseSubsystem => FASEDBridge(port.passthrough_clock_reset.clock, axi4, port.passthrough_clock_reset.reset.asBool, + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) + case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design") + } } - } + }) }) Nil diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index de9e9cf7..51f18227 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -59,26 +59,13 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large") class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") - -// Tweaks that are generally applied to all firesim configs -class WithFireSimConfigTweaks extends Config( +class WithFireSimConfigTweaksWithoutClocking extends Config( // Required: Bake in the default FASED memory model new WithDefaultMemModel ++ // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset new WithFireSimSimpleClocks ++ // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source new WithBootROM ++ - // Optional*: Removing this will require adjusting the UART baud rate and - // potential target-software changes to properly capture UART output - new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ - // Optional: These three configs put the DRAM memory system in it's own clock domian. - // Removing the first config will result in the FASED timing model running - // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. - // 1 GHz matches the FASED default, using some other frequency will require - // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. - new chipyard.config.WithMemoryBusFrequency(1000.0) ++ - new chipyard.config.WithAsynchrousMemoryBusCrossing ++ - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Required: Existing FAME-1 transform cannot handle black-box clock gates new WithoutClockGating ++ // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) @@ -99,6 +86,23 @@ class WithFireSimConfigTweaks extends Config( new chipyard.config.WithNoDebug ) +// Tweaks that are generally applied to all firesim configs +class WithFireSimConfigTweaks extends Config( + // Optional*: Removing this will require adjusting the UART baud rate and + // potential target-software changes to properly capture UART output + new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + // Optional: These three configs put the DRAM memory system in it's own clock domian. + // Removing the first config will result in the FASED timing model running + // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades. + // 1 GHz matches the FASED default, using some other frequency will require + // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ + new chipyard.config.WithAsynchrousMemoryBusCrossing ++ + new testchipip.WithAsynchronousSerialSlaveCrossing ++ + // Tweaks that are independent from multi-clock + new WithFireSimConfigTweaksWithoutClocking +) + /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being * simulated. @@ -216,65 +220,28 @@ class FireSim16LargeBoomConfig extends Config( new boom.common.WithNLargeBooms(16) ++ new chipyard.config.AbstractConfig) +class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ class WithOffchipAXINoClksSetup(pbusFreqMHz: BigInt = 3200) extends Config( - // normal bridges + new offchip bridge - new WithNICBridge ++ - new WithUARTBridge ++ - new WithBlockDeviceBridge ++ - new WithOffchipNetworkSerialAXIBridge ++ // NEW BRIDGE COMBINING SERIAL/AXI - new WithFireSimMultiCycleRegfile ++ - new WithFireSimFAME5 ++ - //new WithTracerVBridge ++ - new WithFireSimIOCellModels ++ - - // new tweaks - // Required: Bake in the default FASED memory model - new WithDefaultMemModel ++ - // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset - new WithFireSimSimpleClocks ++ - // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source - new WithBootROM ++ - // Required: Existing FAME-1 transform cannot handle black-box clock gates - new WithoutClockGating ++ - // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) - new WithoutTLMonitors ++ - // Optional: Adds IO to attach tracerV bridges - //new chipyard.config.WithTraceIO ++ - // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1) - new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ - // Optional: Removing this will require using an initramfs under linux - new testchipip.WithBlockDevice ++ - // Required*: Scale default baud rate with periphery bus frequency - // Rough math... - // NEW: - // pbus @ 500MHz.... baud @ 576000 = 115200 * 5 (somehow the default was 100M) - // OLD: pbus @ 3200MHz, HW baud @ 3686400L AKA 115200 * 32 - // OLD: Linux @ 115200, SBI @ 115200 - // scale down to 100MHz before multipling up //new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++ new chipyard.config.WithUART(BigInt(3686400L)) ++ - // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock) - new chipyard.config.WithNoDebug ) -class WithTracerV extends Config( - new WithTracerVBridge ++ - new chipyard.config.WithTraceIO) - -class FireSimDebugOffchipConfig extends Config( - new WithTracerV ++ - new WithOffchipAXINoClksSetup(3200) ++ - new chipyard.DebugOffchipConfig -) - -class FireSimDebugOffchip2Config extends Config( - new WithTracerV ++ - new WithOffchipAXINoClksSetup(3200) ++ - new chipyard.DebugOffchip2Config -) +//class FireSimDebugOffchipConfig extends Config( +// new WithTracerV ++ +// new WithOffchipAXINoClksSetup(3200) ++ +// new chipyard.DebugOffchipConfig +//) +// +//class FireSimDebugOffchip2Config extends Config( +// new WithTracerV ++ +// new WithOffchipAXINoClksSetup(3200) ++ +// new chipyard.DebugOffchip2Config +//) class FireSimDebugOffchip3Config extends Config( - new WithTracerV ++ - new WithOffchipAXINoClksSetup(4000) ++ + new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking new chipyard.DebugOffchip3Config ) diff --git a/generators/testchipip b/generators/testchipip index abc5be8e..b66dd655 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit abc5be8ef1dc9bb5614ef81fbb021b51a21679dd +Subproject commit b66dd655a3605ff0b3327b133513e27b590d926e