diff --git a/README.md b/README.md index 7e44cc11..a21b142e 100644 --- a/README.md +++ b/README.md @@ -84,6 +84,7 @@ These additional publications cover many of the internal components used in Chip * **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192). * **VLSI** * **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html). + * **Hammer**: H. Liew, et al., *DAC'22*. [PDF](https://dl.acm.org/doi/abs/10.1145/3489517.3530672). ## Acknowledgements diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index ddeda299..5544a4ae 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc CONFIG=TinyRocketConfig - ./build/drc-rundir/generated-scripts/view-drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc make lvs CONFIG=TinyRocketConfig - ./build/lvs-rundir/generated-scripts/view-lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 0b371c26..62e1659b 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -1,7 +1,7 @@ .. _sky130-commercial-tutorial: -Sky130 Tutorial -=============== +Sky130 Commercial Tutorial +========================== The ``vlsi`` folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. Project Structure @@ -121,6 +121,15 @@ The command ``make buildfile`` generates a set of Make targets in ``build/hammer It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. +The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources +and (2) the mapping of memory instances in the design to SRAM macros; +all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +Note that the files in ``generated-src`` vary for each tool/technology flow. +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows +(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate +chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. + + For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-commercial``, which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows: @@ -161,9 +170,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc tutorial=sky130-commercial - ./build/drc-rundir/generated-scripts/view_drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-commercial - ./build/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 7a7a9aa3..7dfda235 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -148,6 +148,15 @@ The command ``make buildfile`` generates a set of Make targets in ``build/hammer It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. +The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources +and (2) the mapping of memory instances in the design to SRAM macros; +all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +Note that the files in ``generated-src`` vary for each tool/technology flow. +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows +(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate +chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. + + For the sake of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``, which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows: @@ -184,7 +193,7 @@ Hammer generates a convenient script to launch these sessions .. code-block:: shell - cd ./build/par-rundir + cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated-scripts/open_chip Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout, @@ -199,7 +208,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin .. code-block:: shell - cd build/par-rundir + cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated_scripts/open_chip -h " Usage: ./generated-scripts/open_chip [-t] [openroad_db_name] @@ -215,7 +224,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin # load post-clock tree database with timing inforamtion ./generated_scripts/open_chip -t post_clock_tree -.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. +Various reports, including timing reports, are found in ``build/par-rundir/reports``. See the `OpenROAD tool plugin `__ for the full list of OpenROAD tool steps and their implementations. @@ -232,9 +241,9 @@ To run DRC & LVS in Magic & Netgen, respectively: .. code-block:: shell make drc tutorial=sky130-openroad - ./build/drc-rundir/generated-scripts/view_drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-openroad - ./build/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Note that in ``sky130-openroad.yml`` we have set the following YAML keys: diff --git a/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png b/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png index 228c708d..2f399e2b 100644 Binary files a/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png and b/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png differ diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 8aafe8c0..dbcadab0 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints: right: 0 top: 0 bottom: 0 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 550 y: 25 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1" type: hardmacro x: 550 y: 270 orientation: "r0" top_layer: "M4" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2" type: hardmacro x: 675 y: 25 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3" type: hardmacro x: 675 y: 270 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 125 y: 150 orientation: "my" top_layer: "M4" master: "SRAM1RW64x21" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 0 y: 25 orientation: "my" top_layer: "M4" master: "SRAM1RW1024x32" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" - type: hardmacro - x: 0 - y: 260 - orientation: "my" - top_layer: "M4" - master: "SRAM1RW1024x37" # Pin placement constraints vlsi.inputs.pin_mode: generated diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index 6edca4d6..b2ecfb26 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,149 +2,18 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "5ns", uncertainty: "1ns"} + {name: "clock_clock", period: "30ns", uncertainty: "2ns"} ] -# Power Straps -par.power_straps_mode: generate -par.generate_power_straps_method: by_tracks -par.blockage_spacing: 40.0 -par.blockage_spacing_top_layer: met4 -par.generate_power_straps_options: - by_tracks: - strap_layers: - - met4 - - met5 - pin_layers: - - met5 - blockage_spacing_met2: 4.0 - blockage_spacing_met4: 2.0 - track_width: 3 - track_width_met5: 1 - track_spacing: 5 - track_start: 10 - track_start_met5: 1 - power_utilization: 0.1 - power_utilization_met4: 0.1 - power_utilization_met5: 0.1 - # Placement Constraints -vlsi.inputs.placement_constraints: - - path: "ChipTop" - type: toplevel - x: 0 - y: 0 - width: 4000 - height: 2500 - margins: - left: 0 - right: 0 - top: 0 - bottom: 0 - - # Place data cache SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 100 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" - type: hardmacro - x: 50 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" - type: hardmacro - x: 50 - y: 1300 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" - type: hardmacro - x: 50 - y: 1900 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" - type: hardmacro - x: 1000 - y: 1900 - orientation: r0 - - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" - type: hardmacro - x: 1000 - y: 1300 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" - type: hardmacro - x: 1000 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" - type: hardmacro - x: 1000 - y: 100 - orientation: r0 - - # Place instruction cache SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 3250 - y: 100 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" - type: hardmacro - x: 3250 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" - type: hardmacro - x: 3450 - y: 1300 - orientation: r0 - - # Place L2 TLB SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" - type: hardmacro - x: 2000 - y: 1300 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" - type: hardmacro - x: 2000 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" - type: hardmacro - x: 2750 - y: 1300 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" - type: hardmacro - x: 2750 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" - type: hardmacro - x: 3460 - y: 1900 - orientation: "r0" - -# Pin placement constraints -vlsi.inputs.pin_mode: generated -vlsi.inputs.pin.generate_mode: semi_auto -vlsi.inputs.pin.assignments: [ - {pins: "*", layers: ["met2", "met4"], side: "bottom"} -] +# If overriding the placement constraints in example-sky130.yml, +# ensure one of the toplevel margin sides corresponding with the power pin metal layers +# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail). +# For example, in example-sky130.yml we set +# par.generate_power_straps_options.by_tracks.pin_layers: 'met5' # horizontal layer +# therefore we must also set: +# vlsi.inputs.placement_constraints: +# - path: "ChipTop" +# ... +# margins: +# right: 0 # or left: 0 \ No newline at end of file diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 62c2aca4..b52266b4 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,9 +3,42 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_clock", period: "30ns", uncertainty: "1ns"} + {name: "clock_clock", period: "50ns", uncertainty: "2ns"} ] +# Flow parameters that yield a routable design with reasonable timing +par.openroad: + timing_driven: true # set to false to drastically speed up runs + create_archive_mode: none + + write_reports: true # set to false to slightly speed up runs + + floorplan_mode: generate + + macro_placement.halo: [50, 50] + + global_placement.timing_driven: true + global_placement.routability_driven: true + + global_placement.placement_padding: 6 + detailed_placement.placement_padding: 4 + clock_tree.placement_padding: 2 + clock_tree_resize.placement_padding: 0 + + clock_tree_resize.setup_margin: 0.0 + clock_tree_resize.hold_margin: 0.20 + global_route_resize.hold_margin: 0.60 + clock_tree_resize.hold_max_buffer_percent: 80 + + global_placement.routing_adjustment: 0.5 + global_route.routing_adjustment: 0.3 + global_route_resize.routing_adjustment: 0.2 + +# DRC/LVS configuration +drc.magic.generate_only: true +lvs.netgen.generate_only: true + + # Placement Constraints vlsi.inputs.placement_constraints: - path: "ChipTop" @@ -13,78 +46,47 @@ vlsi.inputs.placement_constraints: x: 0 y: 0 width: 4000 - height: 2500 + height: 3000 margins: left: 10 - right: 10 + right: 0 top: 10 bottom: 10 - # Place data cache SRAM instances - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0" + # Place SRAM memory instances + # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag + # data cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 100 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0" + y: 50 + orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 700 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0" + y: 450 + orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 1300 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0" + y: 850 + orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 - y: 1900 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0" + y: 1250 + orientation: r90 + + # tag array + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro - x: 1000 - y: 1900 - orientation: r0 + x: 50 + y: 1600 + orientation: r90 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0" + # instruction cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" type: hardmacro - x: 1000 - y: 1300 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0" - type: hardmacro - x: 1000 - y: 700 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0" - type: hardmacro - x: 1000 - y: 100 - orientation: r0 - - # Place instruction cache SRAM instances - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0" - type: hardmacro - x: 3250 - y: 100 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0" - type: hardmacro - x: 3250 - y: 700 - orientation: r0 - - - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0" - type: hardmacro - x: 3450 - y: 1300 - orientation: r0 + x: 50 + y: 2100 + orientation: r90 diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 6afe22a1..5481c4a8 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -20,31 +20,55 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "10ns", uncertainty: "1ns"} + {name: "clock_clock", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow vlsi.core.build_system: make + # Placement Constraints vlsi.inputs.placement_constraints: - path: "ChipTop" type: toplevel x: 0 y: 0 - width: 3500 - height: 2500 + width: 4000 + height: 3000 margins: left: 10 - right: 10 + right: 0 top: 10 bottom: 10 + # Place SRAM memory instances + # data cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 50 + orientation: r90 + + # tag array + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 1600 + orientation: r90 + + # instruction cache + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 2100 + orientation: r90 + + # Power Straps par.power_straps_mode: generate par.generate_power_straps_method: by_tracks -par.blockage_spacing: 40.0 -par.blockage_spacing_top_layer: met4 +par.blockage_spacing: 2.0 +par.blockage_spacing_top_layer: met3 par.generate_power_straps_options: by_tracks: strap_layers: @@ -63,6 +87,7 @@ par.generate_power_straps_options: power_utilization_met4: 0.1 power_utilization_met5: 0.1 + # Pin placement constraints vlsi.inputs.pin_mode: generated vlsi.inputs.pin.generate_mode: semi_auto @@ -70,5 +95,6 @@ vlsi.inputs.pin.assignments: [ {pins: "*", layers: ["met2", "met4"], side: "bottom"} ] + # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler" diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index f9e323bd..902657b8 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit f9e323bd64b8cc79ab810b9761226e9de768f237 +Subproject commit 902657b8bdba7aec12726d6d3c85a2639a4030ad diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index b3d88741..ed910565 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -1,10 +1,7 @@ ######################################################################################### # makefile variables for Hammer tutorials ######################################################################################### -# tutorial ?= none -tutorial ?= sky130-openroad - -extra ?= +tutorial ?= none # TODO: eventually have asap7 commercial/openroad tutorial flavors ifeq ($(tutorial),asap7) @@ -39,5 +36,3 @@ ifeq ($(tutorial),sky130-openroad) # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. ENABLE_YOSYS_FLOW = 1 endif - -HAMMER_EXTRA_ARGS ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)