diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst
index 67165912..dee427cd 100644
--- a/docs/VLSI/ASAP7-Tutorial.rst
+++ b/docs/VLSI/ASAP7-Tutorial.rst
@@ -152,7 +152,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post
 
 Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
 
-Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
+Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + FSDB (or VPD if the ``USE_VPD`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
 
 Power/Rail Analysis
 ^^^^^^^^^^^^^^^^^^^
diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst
index 3eda756a..e8ef5fc0 100644
--- a/docs/VLSI/Sky130-Commercial-Tutorial.rst
+++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst
@@ -156,7 +156,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post
 
 Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
 
-Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
+Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + FSDB (or VPD if the ``USE_VPD`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
 
 Power/Rail Analysis
 ^^^^^^^^^^^^^^^^^^^
diff --git a/vcs.mk b/vcs.mk
index 2a88d39b..6b5eb80b 100644
--- a/vcs.mk
+++ b/vcs.mk
@@ -1,10 +1,10 @@
 HELP_COMPILATION_VARIABLES += \
-"   USE_FSDB               = set to '1' to build VCS simulator to emit FSDB instead of VPD."
+"   USE_VPD                = set to '1' to build VCS simulator to emit VPD instead of FSDB."
 
 HELP_SIMULATION_VARIABLES += \
-"   USE_FSDB               = set to '1' to run VCS simulator emitting FSDB instead of VPD."
+"   USE_VPD                = set to '1' to run VCS simulator emitting VPD instead of FSDB."
 
-ifdef USE_FSDB
+ifndef USE_VPD
 WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
 else
 WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
@@ -66,6 +66,6 @@ PREPROC_DEFINES = \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
 	+define+RANDOMIZE_INVALID_ASSIGN
 
-ifdef USE_FSDB
+ifndef USE_VPD
 PREPROC_DEFINES += +define+FSDB
 endif
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 80ea52b0..3f50b6dc 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -177,7 +177,7 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo
 	echo "  saif.mode: 'time'" >> $@
 	echo "  saif.start_time: '0ns'" >> $@
 	echo "  saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
-ifdef USE_FSDB
+ifndef USE_VPD
 	echo "  options:" >> $@
 	echo '    - "-kdb"' >> $@
 	echo "  options_meta: 'append'" >> $@
@@ -202,7 +202,7 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi
 	echo "  database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
 ifneq ($(BINARY), )
 	echo "  waveforms: [" >> $@
-ifdef USE_FSDB
+ifndef USE_VPD
 	echo "    '$(sim_out_name).fsdb'" >> $@
 else
 	echo "    '$(sim_out_name).vpd'" >> $@