From fb357828415d513e36a410259cdefdd707a23f07 Mon Sep 17 00:00:00 2001
From: Harrison Liew <harrisonliew@gmail.com>
Date: Sun, 1 Sep 2019 10:42:49 -0700
Subject: [PATCH] fix incorrect block for syn/par, but still have timing
 violations

---
 vlsi/README.md   | 10 +++++++++-
 vlsi/example.yml | 30 ++++++++++++++++++++----------
 2 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/vlsi/README.md b/vlsi/README.md
index 0ee8978d..05179ca6 100644
--- a/vlsi/README.md
+++ b/vlsi/README.md
@@ -18,7 +18,15 @@ make buildfile
 ```
 
 # Example design
-In this example, you will be running a SHA-3 accelerator through the VLSI flow. It is assumed that you have already run through the flow to elaborate the Chisel into Verilog.
+In this example, you will be running a SHA-3 accelerator through the VLSI flow. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system:
+```shell
+export MACROCOMPILER_MODE=' --mode synflops'
+export CONFIG=Sha3RocketConfig
+export TOP=Sha3Accel
+make buildfile
+```
+Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead.
+>>>>>>> fix incorrect block for syn/par, but still have timing violations
 
 HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself.
 
diff --git a/vlsi/example.yml b/vlsi/example.yml
index 5711e71a..ffa7e732 100644
--- a/vlsi/example.yml
+++ b/vlsi/example.yml
@@ -2,8 +2,10 @@
 # Technology used is ASAP7
 vlsi.core.technology: asap7
 vlsi.core.node: 7
-technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL"
-technology.asap7.install_dir: "SPECIFY EXTRACTED DIR HERE IF NOT USING TARBALL"
+# Specify dir with ASAP7 tarball
+technology.asap7.tarball_dir: "/tools/B/asap7"
+# Specify extracted dir here if not using tarball
+technology.asap7.install_dir: "/tools/B/asap7"
 
 vlsi.core.max_threads: 12
 
@@ -13,16 +15,17 @@ vlsi.inputs.supplies.VDD: "0.7 V"
 
 # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
 vlsi.inputs.power_spec_mode: "auto"
+vlsi.inputs.power_spec_type: "cpf"
 
 # Specify the setup and hold corners for ASAP7
 vlsi.inputs.mmmc_corners: [
-    {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"},
-    {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"}
+  {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"},
+  {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"}
 ]
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-    {name: "clock", period: "10ns", uncertainty: "0.1ns"}
+  {name: "clock", period: "20ns", uncertainty: "0.1ns"}
 ]
 
 # Generate Make include to aid in flow 
@@ -50,18 +53,25 @@ par.generate_power_straps_options:
 
 # Placement Constraints
 vlsi.inputs.placement_constraints:
-  - path: "ExampleTop"
+  - path: "Sha3Accel"
     type: "toplevel"
     x: 0
     y: 0
-    width: 50
-    height: 50
+    width: 500
+    height: 500
     margins:
       left: 0
       right: 0
       top: 0
       bottom: 0
 
+# Pin placement constraints
+vlsi.inputs.pin_mode: generated
+vlsi.inputs.pin.generate_mode: semi_auto
+vlsi.inputs.pin.assignments: [
+  {pins: "*", layers: ["M5", "M7"], side: "bottom"}
+]
+
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "sram_compiler"
 vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]
@@ -82,6 +92,6 @@ par.innovus.design_flow_effort: "standard"
 par.inputs.gds_merge: true
 # Calibre options
 vlsi.core.drc_tool: "calibre"
-vlsi.core.drc_tool_path: ["hammer-cad-plugins/drc"]
+vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
 vlsi.core.lvs_tool: "calibre"
-vlsi.core.lvs_tool_path: ["hammer-cad-plugins/lvs"]
+vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]