diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 126766c4..edae3ac9 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -24,6 +24,10 @@ Processor Cores An in-order RISC-V core written in System Verilog. Previously called Ariane. See :ref:`Generators/CVA6:CVA6 Core` for more information. +**Ibex Core** + An in-order RISC-V core writeen in System Verilog. + See :ref:`Generators/Ibex:Ibex Core` for more information. + Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/Generators/Ibex.rst b/docs/Generators/Ibex.rst new file mode 100644 index 00000000..2b958358 --- /dev/null +++ b/docs/Generators/Ibex.rst @@ -0,0 +1,14 @@ +Ibex Core +==================================== + +`Ibex `__ is a parameterizable RV32 embedded core written in SystemVerilog, currently maintained by lowRISC. +The `Ibex core` is wrapped in an `Ibex tile` so it can be used with the `Rocket Chip SoC generator`. +The core exposes a custom memory interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. + +.. Warning:: The Ibex mtvec register is 256 byte aligned. When writing/running tests, ensure that the trap vector is also 256 byte aligned. + +.. Warning:: The Ibex reset vector is located at 0x80. + +While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available. + +For more information, see the `GitHub repository `__. \ No newline at end of file diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 6f11c875..22d7ad40 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -28,6 +28,7 @@ so changes to the generators themselves will automatically be used when building SiFive-Generators SHA3 CVA6 + Ibex NVDLA Sodor