From e78756704bcd2d2605bd845df6d37b41301a6dac Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 18:14:50 -0800 Subject: [PATCH 1/8] FIX: fix vcu118 sd card frequency --- fpga/src/main/resources/vcu118/sdboot/sd.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index f1bdb61e..60bebbd8 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -22,7 +22,7 @@ #error Must define TL_CLK #endif -#define F_CLK TL_CLK +#define F_CLK (TL_CLK) static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); @@ -79,7 +79,9 @@ static inline void sd_cmd_end(void) static void sd_poweron(void) { long i; - REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + // HACK: frequency change + // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); + REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5); REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; for (i = 10; i > 0; i--) { sd_dummy(); @@ -176,7 +178,9 @@ static int copy(void) // TODO: Speed up SPI freq. (breaks between these two values) //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); - REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); + // HACK: frequency change + // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); + REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); // / 0.5 if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { sd_cmd_end(); return 1; From 069a9d2999d53b26550387506097c38fc420c4a3 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 5 Dec 2023 15:07:25 -0800 Subject: [PATCH 2/8] ADD: add equation for setting certain SPI clock speed --- fpga/src/main/resources/vcu118/sdboot/sd.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index 60bebbd8..e8d45ba7 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -22,7 +22,14 @@ #error Must define TL_CLK #endif -#define F_CLK (TL_CLK) +#define F_CLK (TL_CLK) + +// SPI SCLK frequency, in kHz +#define SPI_CLK 1250 + +// SPI clock divisor value +// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi +#define SPI_DIV (((F_CLK * 1000) / SPI_CLK) / 2 - 1) static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR); @@ -80,8 +87,8 @@ static void sd_poweron(void) { long i; // HACK: frequency change - // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL); - REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5); + + REG32(spi, SPI_REG_SCKDIV) = SPI_DIV; REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF; for (i = 10; i > 0; i--) { sd_dummy(); @@ -173,14 +180,10 @@ static int copy(void) dputs("CMD18"); - kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B); + kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B); kprintf("LOADING "); - // TODO: Speed up SPI freq. (breaks between these two values) - //REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL); - // HACK: frequency change - // REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL); - REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); // / 0.5 + REG32(spi, SPI_REG_SCKDIV) = SPI_DIV; if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) { sd_cmd_end(); return 1; From 733bd3e7eaadd071e6e0f9653ebcaf33ef725636 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Dec 2023 12:03:50 -0800 Subject: [PATCH 3/8] Bump testchipip for more organized package --- generators/caliptra-aes-acc | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 16 ++++++------- .../chipyard/src/main/scala/Subsystem.scala | 2 +- .../main/scala/clocking/HasChipyardPRCI.scala | 3 ++- .../main/scala/clocking/TLClockDivider.scala | 4 ++-- .../main/scala/clocking/TLClockSelector.scala | 4 ++-- .../main/scala/config/AbstractConfig.scala | 14 ++++++----- .../src/main/scala/config/ChipConfigs.scala | 24 +++++++++---------- .../scala/config/MemorySystemConfigs.scala | 4 ++-- .../src/main/scala/config/NoCoreConfigs.scala | 4 ++-- .../config/PeripheralDeviceConfigs.scala | 22 ++++++++--------- .../src/main/scala/config/SodorConfigs.scala | 12 +++++----- .../src/main/scala/config/SpikeConfigs.scala | 2 +- .../main/scala/config/TracegenConfigs.scala | 2 +- .../config/fragments/ClockingFragments.scala | 4 +--- .../config/fragments/TileFragments.scala | 2 +- .../src/main/scala/example/FlatChipTop.scala | 2 +- .../main/scala/example/FlatTestHarness.scala | 5 +++- .../main/scala/harness/HarnessBinders.scala | 9 ++++++- .../src/main/scala/iobinders/IOBinders.scala | 8 ++++++- .../src/main/scala/iobinders/Ports.scala | 8 +++++-- generators/testchipip | 2 +- 22 files changed, 88 insertions(+), 67 deletions(-) diff --git a/generators/caliptra-aes-acc b/generators/caliptra-aes-acc index 15d2f852..82fa7080 160000 --- a/generators/caliptra-aes-acc +++ b/generators/caliptra-aes-acc @@ -1 +1 @@ -Subproject commit 15d2f85262125a3ba5a674868d4bcbdfbf720df1 +Subproject commit 82fa7080f428b2e59062a55e948f507805c98ef5 diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index d7263008..01b6626d 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,13 +13,13 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem - with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport - with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin - with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register - with testchipip.CanHaveTraceIO // Enables optionally adding trace IO - with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad - with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device - with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport + with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin + with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register + with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO + with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad + with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device + with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART @@ -40,7 +40,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with testchipip.CanHaveTraceIOModuleImp + with testchipip.cosim.CanHaveTraceIOModuleImp with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index a3ba679e..8654d561 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile} -import testchipip.{CanHavePeripheryTLSerial, SerialTLKey} +import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} trait CanHaveHTIF { this: BaseSubsystem => // Advertise HTIF if system can communicate with fesvr diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 356a0432..7aa676d5 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -14,7 +14,8 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ -import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer} +import testchipip.boot.{TLTileResetCtrl} +import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala index 45f9374d..a3c33561 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.util.ElaborationArtefacts -import testchipip._ +import testchipip.clocking._ // This module adds a TileLink memory-mapped clock divider to the clock graph // The output clock/reset pairs from this module should be synchronized later @@ -38,7 +38,7 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit val reg = Module(new AsyncResetRegVec(w=divBits, init=0)) println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider") - val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl))) + val divider = Module(new ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl))) divider.io.clockIn := sources(i).clock // busReset is expected to be high for a long time, since reset will take a while to propagate // to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala index 27870428..1d0a149d 100644 --- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala +++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.util.ElaborationArtefacts -import testchipip._ +import testchipip.clocking._ case class ClockSelNode()(implicit valName: ValName) extends MixedNexusNode(ClockImp, ClockGroupImp)( @@ -40,7 +40,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e sel := reg.io.q println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux") - val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux") + val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux") mux.io.sel := sel mux.io.resetAsync := asyncReset.asAsyncReset sinks(i).clock := mux.io.clockOut diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 06f9af3b..cef46e04 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -61,12 +61,14 @@ class AbstractConfig extends Config( new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus - new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address - new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address - new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( // add a serial-tilelink interface - client = Some(testchipip.SerialTLClientParams(idBits = 4)), // serial-tilelink interface will master the FBUS, and support 4 idBits - width = 32 // serial-tilelink interface with 32 lanes - ))) ++ + new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address + new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address + new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface + testchipip.serdes.SerialTLParams( + client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits + width = 32 // serial-tilelink interface with 32 lanes + ) + )) ++ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index e3d18375..ffcb3f77 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -3,7 +3,7 @@ package chipyard import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem.{MBUS, SBUS} -import testchipip.{OBUS} +import testchipip.soc.{OBUS} // A simple config demonstrating how to set up a basic chip in Chipyard class ChipLikeRocketConfig extends Config( @@ -22,16 +22,16 @@ class ChipLikeRocketConfig extends Config( //================================== // Set up I/O //================================== - new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO - new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory + new testchipip.serdes.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO + new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // Remove axi4 mem port new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel //================================== // Set up buses //================================== - new testchipip.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory - new testchipip.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory + new testchipip.soc.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory + new testchipip.soc.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory //================================== // Set up clock./reset @@ -60,17 +60,17 @@ class ChipBringupHostConfig extends Config( //============================= // Setup the SerialTL side on the bringup device //============================= - new testchipip.WithSerialTLWidth(4) ++ // match width with the chip - new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host - idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000 - new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock + new testchipip.serdes.WithSerialTLWidth(4) ++ // match width with the chip + new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host + idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000 + new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock //============================ // Setup bus topology on the bringup system //============================ - new testchipip.WithOffchipBusClient(SBUS, // offchip bus hangs off the SBUS + new testchipip.soc.WithOffchipBusClient(SBUS, // offchip bus hangs off the SBUS blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly - new testchipip.WithOffchipBus ++ // offchip bus + new testchipip.soc.WithOffchipBus ++ // offchip bus //============================= // Set up memory on the bringup system @@ -80,7 +80,7 @@ class ChipBringupHostConfig extends Config( //============================= // Generate the TSI-over-UART side of the bringup system //============================= - new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++ // nonstandard baud rate to improve performance + new testchipip.tsi.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++ // nonstandard baud rate to improve performance //============================= // Set up clocks of the bringup system diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala index aab7fb7f..c49f85ee 100644 --- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala @@ -19,14 +19,14 @@ class GB1MemoryRocketConfig extends Config( // DOC include start: mbusscratchpadrocket class MbusScratchpadOnlyRocketConfig extends Config( - new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad + new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket class SbusScratchpadRocketConfig extends Config( - new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad + new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 19e9a7e0..4f70f9ee 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -4,8 +4,8 @@ import org.chipsalliance.cde.config.{Config} // A empty config with no cores. Useful for testing class NoCoresConfig extends Config( - new testchipip.WithNoBootAddrReg ++ - new testchipip.WithNoCustomBootPin ++ + new testchipip.boot.WithNoBootAddrReg ++ + new testchipip.boot.WithNoCustomBootPin ++ new chipyard.config.WithNoCLINT ++ new chipyard.config.WithNoBootROM ++ new chipyard.config.WithBroadcastManager ++ diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 5473b99e..99400743 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -22,13 +22,13 @@ class SmallSPIFlashRocketConfig extends Config( class SimBlockDeviceRocketConfig extends Config( new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice - new testchipip.WithBlockDevice ++ // add block-device module to peripherybus + new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) class BlockDeviceModelRocketConfig extends Config( new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel - new testchipip.WithBlockDevice ++ // add block-device module to periphery bus + new testchipip.iceblk.WithBlockDevice ++ // add block-device module to periphery bus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -53,10 +53,10 @@ class MMIORocketConfig extends Config( class LBWIFRocketConfig extends Config( new chipyard.config.WithOffchipBusFrequency(500) ++ - new testchipip.WithOffchipBusClient(MBUS) ++ - new testchipip.WithOffchipBus ++ - new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory + new testchipip.soc.WithOffchipBusClient(MBUS) ++ + new testchipip.soc.WithOffchipBus ++ + new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -69,10 +69,10 @@ class dmiRocketConfig extends Config( // DOC include end: DmiRocket class ManyPeripheralsRocketConfig extends Config( - new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new testchipip.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS - new testchipip.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory - new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory + new testchipip.iceblk.WithBlockDevice ++ // add block-device module to peripherybus + new testchipip.soc.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS + new testchipip.soc.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory + new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new chipyard.config.WithSPIFlash ++ // add the SPI flash controller @@ -84,7 +84,7 @@ class ManyPeripheralsRocketConfig extends Config( class UARTTSIRocketConfig extends Config( new chipyard.harness.WithSerialTLTiedOff ++ - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.config.WithMemoryBusFrequency(10) ++ new chipyard.config.WithFrontBusFrequency(10) ++ new chipyard.config.WithPeripheryBusFrequency(10) ++ diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 4181083c..7d7c7ac3 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -16,7 +16,7 @@ class Sodor1StageConfig extends Config( class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -25,7 +25,7 @@ class Sodor2StageConfig extends Config( class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -34,7 +34,7 @@ class Sodor3StageConfig extends Config( class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -43,7 +43,7 @@ class Sodor3StageSinglePortConfig extends Config( class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -52,7 +52,7 @@ class Sodor5StageConfig extends Config( class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.serdes.WithSerialTLWidth(32) ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 4c1fc303..6f4c6ab7 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -43,7 +43,7 @@ class SpikeUltraFastDevicesConfig extends Config( new chipyard.harness.WithSimBlockDevice ++ new chipyard.harness.WithLoopbackNIC ++ new icenet.WithIceNIC ++ - new testchipip.WithBlockDevice ++ + new testchipip.iceblk.WithBlockDevice ++ new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 55cce1b8..4235bf1e 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -43,6 +43,6 @@ class NonBlockingTraceGenL2Config extends Config( class NonBlockingTraceGenL2RingConfig extends Config( new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ - new testchipip.WithRingSystemBus ++ + new testchipip.soc.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new AbstractTraceGenConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 9191bc0c..f86254c4 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -13,9 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams} import chipyard._ import chipyard.clocking._ -import testchipip.{OffchipBusKey} - -import testchipip.{OffchipBusKey} +import testchipip.soc.{OffchipBusKey} // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 6262fbcd..92d8fc6f 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -11,7 +11,7 @@ import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} import sodor.common.{SodorTileAttachParams} import ibex.{IbexTileAttachParams} -import testchipip._ +import testchipip.cosim.{TracePortKey, TracePortParams} import barf.{TilePrefetchingMasterPortParams} class WithL2TLBs(entries: Int) extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index 24fcad8e..96139ef5 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -14,7 +14,7 @@ import chipyard.harness.{BuildTop} import chipyard.clocking._ import chipyard.iobinders._ import barstools.iocell.chisel._ -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} class WithFlatChipTop extends Config((site, here, up) => { case BuildTop => (p: Parameters) => new FlatChipTop()(p) diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 5f6c69f1..304c58a3 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -11,7 +11,10 @@ import freechips.rocketchip.util.{PlusArg} import freechips.rocketchip.subsystem.{CacheBlockBytes} import freechips.rocketchip.devices.debug.{SimJTAG} import freechips.rocketchip.jtag.{JTAGIO} -import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI} +import testchipip.serdes.{SerialTLKey} +import testchipip.uart.{UARTAdapter} +import testchipip.dram.{SimDRAM} +import testchipip.tsi.{TSIHarness, SimTSI} import chipyard.harness.{BuildTop} // A "flat" TestHarness that doesn't use IOBinders diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 94321506..9748f597 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -12,7 +12,14 @@ import freechips.rocketchip.util._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.devices.debug.{SimJTAG} import barstools.iocell.chisel._ -import testchipip._ +import testchipip.dram.{SimDRAM} +import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO} +import testchipip.soc.{TestchipSimDTM} +import testchipip.spi.{SimSPIFlashModel} +import testchipip.uart.{UARTAdapter} +import testchipip.serdes.{UARTToSerial, SerialWidthAdapter} +import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel} +import testchipip.cosim.{SpikeCosim} import icenet.{NicLoopback, SimNetwork} import chipyard._ import chipyard.clocking.{HasChipyardPRCI} diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 7894ba51..45f72641 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -23,7 +23,13 @@ import tracegen.{TraceGenSystemModuleImp} import barstools.iocell.chisel._ -import testchipip._ +import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} +import testchipip.spi.{SPIChipIO} +import testchipip.boot.{CanHavePeripheryCustomBootPin} +import testchipip.util.{ClockedIO} +import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO} +import testchipip.cosim.{CanHaveTraceIOModuleImp, TraceOutputTop, SpikeCosimConfig} +import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule} diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index c5c9f19e..ba14cc39 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -4,9 +4,13 @@ import chisel3._ import chisel3.experimental.{Analog} import sifive.blocks.devices.uart.{UARTPortIO} import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO} -import sifive.blocks.devices.i2c.{I2CPort} import sifive.blocks.devices.gpio.{GPIOPortIO} -import testchipip._ +import testchipip.util.{ClockedIO} +import testchipip.serdes.{TLSerdesser, SerialIO, SerialTLParams} +import testchipip.spi.{SPIChipIO} +import testchipip.cosim.{TraceOutputTop, SpikeCosimConfig} +import testchipip.iceblk.{BlockDeviceIO, BlockDeviceConfig} +import testchipip.tsi.{UARTTSIIO} import icenet.{NICIOvonly, NICConfig} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters} diff --git a/generators/testchipip b/generators/testchipip index 50a05b07..17109544 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 50a05b078295f91798bee9d506a47a4e967dd493 +Subproject commit 171095445e15bb8f002fbb3ec8b0f0b26dfcc5fe From 1e5ebf192ad8686c6ec02ceb1ab9cd69cac2aae5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Dec 2023 12:11:12 -0800 Subject: [PATCH 4/8] Update firesim/firechip with new testchipip packaging --- .../src/main/scala/BridgeBinders.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 21 ++++++++++--------- sims/firesim | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index ad643deb..954c104c 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import freechips.rocketchip.util.{ResetCatchAndSync} import sifive.blocks.devices.uart._ -import testchipip._ +import testchipip.tsi.{SerialRAM} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import junctions.{NastiKey, NastiParameters} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 944fe9cf..9f5f7ef6 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -13,7 +13,8 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing} -import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams} +import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig} +import testchipip.cosim.{TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} @@ -101,7 +102,7 @@ class WithFireSimDesignTweaks extends Config( // Required: Bake in the default FASED memory model new WithDefaultMemModel ++ // Optional: reduce the width of the Serial TL interface - new testchipip.WithSerialTLWidth(4) ++ + new testchipip.serdes.WithSerialTLWidth(4) ++ // Required*: Scale default baud rate with periphery bus frequency new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ // Optional: Adds IO to attach tracerV bridges @@ -109,7 +110,7 @@ class WithFireSimDesignTweaks extends Config( // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1) new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // Optional: Removing this will require using an initramfs under linux - new testchipip.WithBlockDevice + new testchipip.iceblk.WithBlockDevice ) // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults @@ -151,7 +152,7 @@ class WithFireSimConfigTweaks extends Config( class WithMinimalFireSimHighPerfConfigTweaks extends Config( new WithFireSimHighPerfClocking ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ - new testchipip.WithMbusScratchpad ++ + new testchipip.soc.WithMbusScratchpad ++ new WithMinimalFireSimDesignTweaks ) @@ -161,8 +162,8 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config( class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config( new WithFireSimHighPerfClocking ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against - new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model - new testchipip.WithBlockDevice(true) ++ // add in block device + new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model + new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device new WithMinimalFireSimDesignTweaks ) @@ -257,11 +258,11 @@ class FireSimSmallSystemConfig extends Config( new WithoutClockGating ++ new WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ - new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( - client = Some(testchipip.SerialTLClientParams(idBits = 4)), + new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( + client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)), width = 32 ))) ++ - new testchipip.WithBlockDevice ++ + new testchipip.iceblk.WithBlockDevice ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ new chipyard.RocketConfig) @@ -339,7 +340,7 @@ class FireSim16LargeBoomConfig extends Config( class FireSimNoMemPortConfig extends Config( new WithDefaultFireSimBridges ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ - new testchipip.WithMbusScratchpad ++ + new testchipip.soc.WithMbusScratchpad ++ new WithFireSimConfigTweaks ++ new chipyard.RocketConfig) diff --git a/sims/firesim b/sims/firesim index 73fe6a51..e9758935 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 73fe6a51b28a2dbbe3f307bdbc6ba2407b311a27 +Subproject commit e975893595129c2682a72fb7e5898273fcc2d071 From 604cb6358f559cac8220a59a9539a084ae11413d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Dec 2023 12:17:00 -0800 Subject: [PATCH 5/8] Bump fpga-platforms to new organized testchipip --- docs/Customization/Memory-Hierarchy.rst | 2 +- fpga/bootrom.rv32.img | Bin 0 -> 192 bytes fpga/bootrom.rv64.img | Bin 0 -> 192 bytes fpga/src/main/scala/arty/Configs.scala | 4 ++-- fpga/src/main/scala/arty100t/Configs.scala | 6 +++--- fpga/src/main/scala/arty100t/HarnessBinders.scala | 2 -- fpga/src/main/scala/nexysvideo/Configs.scala | 6 +++--- .../main/scala/nexysvideo/HarnessBinders.scala | 2 -- fpga/src/main/scala/vc707/Configs.scala | 2 +- fpga/src/main/scala/vcu118/Configs.scala | 2 +- fpga/src/main/scala/vcu118/bringup/Configs.scala | 2 +- .../scala/vcu118/bringup/CustomOverlays.scala | 2 +- .../main/scala/vcu118/bringup/DigitalTop.scala | 2 +- .../scala/vcu118/bringup/HarnessBinders.scala | 2 +- .../src/main/scala/vcu118/bringup/IOBinders.scala | 2 +- .../main/scala/vcu118/bringup/TestHarness.scala | 3 ++- variables.mk | 2 +- 17 files changed, 19 insertions(+), 22 deletions(-) create mode 100755 fpga/bootrom.rv32.img create mode 100755 fpga/bootrom.rv64.img diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 62ccf684..ecb666d1 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -94,7 +94,7 @@ memory channel. Instead of connecting to off-chip DRAM, you can instead connect a scratchpad and remove the off-chip link. This is done by adding a fragment like -``testchipip.WithScratchpad`` to your configuration and removing the +``testchipip.soc.WithScratchpad`` to your configuration and removing the memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``. .. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala diff --git a/fpga/bootrom.rv32.img b/fpga/bootrom.rv32.img new file mode 100755 index 0000000000000000000000000000000000000000..fbab5033ab69b24d54a0175d735a0f2cf21f5364 GIT binary patch literal 192 zcmdna%D_~t>hLj{g_R+np@Chv&6Qy?n*f8d!ZikAHaCW5wPXJu&tm(R&v1Z^0Sgdk zWnd6yW&Kku5NhyQNx)$8B_+qnpM)5aTbLM%1q=*?SsQ?~t3j~>t3feCfI$9-`~Q)R z$^Rh#r+E=8!{d2O|Aa+V88)+SWl&zg%3$uwz`(4^3e+oV0&?GUpgogYTN#Df7&wXz N*nnm!7zhIm0s!cFEFk~@ literal 0 HcmV?d00001 diff --git a/fpga/bootrom.rv64.img b/fpga/bootrom.rv64.img new file mode 100755 index 0000000000000000000000000000000000000000..8d4fea0554d5c5f953b25cfe015ae3c9bd3b1189 GIT binary patch literal 192 zcmdna%D_~t>hLj{g_R+np@Chv&6Qy?n*f8d!ZikAHaCW5wPXJu&tm(R&v1Z^0Sgdk zWnd6yW&Kku5NhyQNx)$8B_+qnpM)5aTbLM%1q=*?SsQ?~t3j~>t3feCfI$9-`~Q)R z$^Rh#r+E=8!{d2O|Aa+V88)+SWl&zg%3$uwz`$(E3e+oV0&?GUpgogYTN#Df7&wXz N*nnm!7zhIm0s!i%EHMB8 literal 0 HcmV?d00001 diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 1bf2b643..eeb26b60 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem} @@ -30,7 +30,7 @@ class WithArtyTweaks extends Config( new chipyard.config.WithFrontBusFrequency(32) ++ new chipyard.config.WithControlBusFrequency(32) ++ new chipyard.config.WithPeripheryBusFrequency(32) ++ - new testchipip.WithNoSerialTL + new testchipip.serdes.WithNoSerialTL ) class TinyRocketArtyConfig extends Config( diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 213425f5..c9892aa8 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ import sifive.fpgashells.shell.{DesignKey} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem} @@ -25,7 +25,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config( new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ new WithNoDesignKey ++ - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++ new chipyard.config.WithMemoryBusFrequency(freqMHz) ++ @@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config( class BringupArty100TConfig extends Config( new WithArty100TSerialTLToGPIO ++ new WithArty100TTweaks(freqMHz = 50) ++ - new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++ + new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++ new chipyard.ChipBringupHostConfig) diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 4c821970..dd7c1a35 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -20,8 +20,6 @@ import chipyard._ import chipyard.harness._ import chipyard.iobinders._ -import testchipip._ - class WithArty100TUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTTSIPort) => { val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index 01b095fa..fe53b96d 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ import sifive.fpgashells.shell.{DesignKey} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem} @@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config( new WithNexysVideoUARTTSI ++ new WithNexysVideoDDRTL ++ new WithNoDesignKey ++ - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new chipyard.config.WithMemoryBusFrequency(50.0) ++ @@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config( new WithNexysVideoUARTTSI ++ new WithNoDesignKey ++ new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR - new testchipip.WithUARTTSIClient ++ + new testchipip.tsi.WithUARTTSIClient ++ new chipyard.harness.WithSerialTLTiedOff ++ new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++ new chipyard.config.WithMemoryBusFrequency(50.0) ++ diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala index 4027cbcf..e6865eff 100644 --- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala +++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala @@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams} import chipyard._ import chipyard.harness._ - -import testchipip._ import chipyard.iobinders._ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({ diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index 124920d7..4842434e 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard.{BuildSystem, ExtTLMem} import chipyard.harness._ diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 32dc3c2c..3f99fdb9 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} -import testchipip.{SerialTLKey} +import testchipip.serdes.{SerialTLKey} import chipyard._ import chipyard.harness._ diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 65a23a1f..0760fa72 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} -import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} +import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} import chipyard.{BuildSystem} diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 4b9604f9..a52a1b5e 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.clocks._ import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} -import testchipip.{TSIHostWidgetIO} +import testchipip.tsi.{TSIHostWidgetIO} import chipyard.fpga.vcu118.{FMCPMap} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index c5401d32..e4efbdc7 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule} class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop with sifive.blocks.devices.i2c.HasPeripheryI2C - with testchipip.HasPeripheryTSIHostWidget + with testchipip.tsi.HasPeripheryTSIHostWidget { override lazy val module = new BringupVCU118DigitalTopModule(this) } diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index d60de620..c130a697 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} -import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} +import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} import chipyard.harness._ import chipyard.iobinders._ diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index 155f2647..24b7aa9a 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} -import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} +import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort} diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 12398d8f..94d28258 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter} +import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO} +import testchipip.util.{TLSinkSetter} import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} diff --git a/variables.mk b/variables.mk index fcda57ef..65f493d2 100644 --- a/variables.mk +++ b/variables.mk @@ -97,7 +97,7 @@ ifeq ($(SUB_PROJECT),testchipip) VLOG_MODEL ?= $(MODEL) MODEL_PACKAGE ?= chipyard.unittest CONFIG ?= TestChipUnitTestConfig - CONFIG_PACKAGE ?= testchipip + CONFIG_PACKAGE ?= testchipip.test GENERATOR_PACKAGE ?= chipyard TB ?= TestDriver TOP ?= UnitTestSuite From b7176b3c29b8437e7ec85ceeb518891a88c2de28 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 19 Dec 2023 15:14:39 -0800 Subject: [PATCH 6/8] Bump testchipip --- .../chipyard/src/main/scala/harness/HarnessBinders.scala | 4 ++-- generators/testchipip | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 9748f597..6710696d 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -16,8 +16,8 @@ import testchipip.dram.{SimDRAM} import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO} import testchipip.soc.{TestchipSimDTM} import testchipip.spi.{SimSPIFlashModel} -import testchipip.uart.{UARTAdapter} -import testchipip.serdes.{UARTToSerial, SerialWidthAdapter} +import testchipip.uart.{UARTAdapter, UARTToSerial} +import testchipip.serdes.{SerialWidthAdapter} import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel} import testchipip.cosim.{SpikeCosim} import icenet.{NicLoopback, SimNetwork} diff --git a/generators/testchipip b/generators/testchipip index 17109544..70e19831 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 171095445e15bb8f002fbb3ec8b0f0b26dfcc5fe +Subproject commit 70e198313a7e467f9219e4caba0158a96f851503 From 516ecf9d9e61fd3ee2cedb1681947bd0bcf6a12c Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 20 Dec 2023 22:16:15 -0800 Subject: [PATCH 7/8] ADD: increase frequency to maximum --- fpga/src/main/resources/vcu118/sdboot/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index e8d45ba7..c89f1556 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -25,7 +25,7 @@ #define F_CLK (TL_CLK) // SPI SCLK frequency, in kHz -#define SPI_CLK 1250 +#define SPI_CLK 25000 // 1250 // SPI clock divisor value // @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi From c32de04b5d0535df406cccc25109311fb08c49ff Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 20 Dec 2023 22:25:05 -0800 Subject: [PATCH 8/8] ADD: add inline docs --- fpga/src/main/resources/vcu118/sdboot/sd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c index c89f1556..bc1a68e8 100644 --- a/fpga/src/main/resources/vcu118/sdboot/sd.c +++ b/fpga/src/main/resources/vcu118/sdboot/sd.c @@ -25,7 +25,9 @@ #define F_CLK (TL_CLK) // SPI SCLK frequency, in kHz -#define SPI_CLK 25000 // 1250 +// We are using the 25MHz High Speed mode. If this speed is not supported by the +// SD card, consider changing to the Default Speed mode (12.5 MHz). +#define SPI_CLK 25000 // SPI clock divisor value // @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi