From 8867c3241c9f3ddeed483f7fa6f35ac44631f42f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 17 Aug 2020 17:07:29 -0700 Subject: [PATCH 01/23] Add .swo to .gitignore | Update docs --- .gitignore | 1 + docs/Simulation/Software-RTL-Simulation.rst | 49 +++++++-------------- 2 files changed, 18 insertions(+), 32 deletions(-) diff --git a/.gitignore b/.gitignore index 35d9b2d8..a85d0dd2 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,7 @@ target *.stamp *.vcd *.swp +*.swo *.log *# *~ diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 28ae223e..ca852d36 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -40,8 +40,7 @@ For a proprietry VCS simulation, enter the ``sims/vcs`` directory # Enter VCS directory cd sims/vcs - -.. _sim-default: +.. _sw-sim-help: Simulating The Default Example ------------------------------- @@ -62,12 +61,6 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. -The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. - -.. code-block:: shell - - make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple - Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -82,6 +75,22 @@ For example: .. _sw-sim-custom: +Makefile Variables and Commands +------------------------------- +You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``: + +.. code-block:: shell + + # Enter Verilator directory + cd sims/verilator + make help + + # Enter VCS directory + cd sims/vcs + make help + +.. _sim-default: + Simulating A Custom Project ------------------------------- @@ -132,29 +141,6 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. -Fast Memory Loading -------------------- - -The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. - -.. code-block:: shell - - make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 - -The ``.hex`` file should be a text file with a hexadecimal number on each line. - -.. code-block:: text - - deadbeef - 0123 - -Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. - -A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. - -.. code-block:: shell - - make run-binary-hex BINARY=test.riscv Generating Waveforms ----------------------- @@ -166,4 +152,3 @@ An open-source vcd-capable waveform viewer is `GTKWave Date: Mon, 17 Aug 2020 20:28:05 -0700 Subject: [PATCH 02/23] Add help section to makefiles + Reorganize --- common.mk | 55 ++++++++---- sims/vcs/Makefile | 111 +++++++++++++++++++++++-- sims/verilator/Makefile | 175 +++++++++++++++++++++++++++++---------- tools/dromajo/dromajo.mk | 3 +- variables.mk | 60 +++++++++----- 5 files changed, 316 insertions(+), 88 deletions(-) diff --git a/common.mk b/common.mk index 43615a92..87d4047c 100644 --- a/common.mk +++ b/common.mk @@ -3,22 +3,46 @@ ######################################################################################### SHELL=/bin/bash - ifndef RISCV $(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file) else $(info Running with RISCV=$(RISCV)) endif +######################################################################################### +# specify user-interface variables +######################################################################################### +HELP_COMPILATION_VARIABLES += \ +" EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ +" EXTRA_SIM_CFLAGS = CFLAGS for building simulators" \ +" EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = requirements to build the simulator" + +EXTRA_GENERATOR_REQS ?= +EXTRA_SIM_CXXFLAGS ?= +EXTRA_SIM_CFLAGS ?= +EXTRA_SIM_LDFLAGS ?= +EXTRA_SIM_SOURCES ?= +EXTRA_SIM_REQS ?= + +#---------------------------------------------------------------------------- +HELP_SIMULATION_VARIABLES += \ +" EXTRA_SIM_FLAGS = runtime simulation flags (passed within +permissive)" + +EXTRA_SIM_FLAGS ?= + +#---------------------------------------------------------------------------- +HELP_COMMANDS += \ +" run-binary = run [./$(shell basename $(sim))] and log instructions to file" \ +" run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ +" run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ +" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" ######################################################################################### -# extra make variables/rules from subprojects -# -# EXTRA_GENERATOR_REQS - requirements needed for the main generator -# EXTRA_SIM_FLAGS - runtime simulation flags -# EXTRA_SIM_CC_FLAGS - cc flags for simulators -# EXTRA_SIM_SOURCES - simulation sources needed for simulator -# EXTRA_SIM_REQS - requirements to build the simulator +# include additional subproject make fragments +# see HELP_COMPILATION_VARIABLES ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk @@ -55,7 +79,6 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ touch $@ - ######################################################################################### # Bloop Project Definitions ######################################################################################### @@ -139,19 +162,19 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-binary-fast run-binary-debug run-fast +.PHONY: run-binary run-binary-fast +.PHONY: run-binary-debug +.PHONY: run-fast + +# run normal binary with hardware-logged insn dissassembly run-binary: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) -######################################################################################### -# helper rules to run simulator as fast as possible -######################################################################################### +# run simulator as fast as possible (no insn disassembly) run-binary-fast: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 14ebae59..46b3a267 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,7 +25,10 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -include $(base_dir)/vcs.mk +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off + +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd .PHONY: default debug default: $(sim) @@ -36,22 +39,97 @@ debug: $(sim_debug) ######################################################################################### include $(base_dir)/common.mk +######################################################################################### +# verilator-specific user-interface variables and commands +######################################################################################### +HELP_COMPILATION_VARIABLES += +HELP_COMMANDS += \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and verilator-generated files" \ +" clean-sim-debug = removes debug simulator and verilator-generated files" + ######################################################################################### # vcs binary and arguments ######################################################################################### VCS = vcs -full64 -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES) +PREPROC_DEFINES = \ + +define+VCS \ + +define+CLOCK_PERIOD=1.0 \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN + +VCS_NONCC_OPTS = \ + -notice \ + -line \ + +lint=all,noVCDE,noONGS,noUI \ + -timescale=1ns/1ps \ + -quiet \ + -q \ + +rad \ + +vcs+lic+wait \ + +vc+list \ + -error=noZMMCM \ + -error=PCWM-L \ + -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ + +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ + +incdir+$(build_dir) \ + $(PREPROC_DEFINES) \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VCS_CXXFLAGS = \ + $(CXXFLAGS) \ + $(CMODE) \ + -I$(VCS_HOME)/include \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -std=c++11 \ + $(EXTRA_SIM_CXXFLAGS) + +VCS_LDFLAGS = \ + $(LDFLAGS) \ + $(CMODE) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VCS_CC_OPTS = \ + -CFLAGS "$(VCS_CXXFLAGS)" \ + -LDFLAGS "$(VCS_LDFLAGS)" + +#---------------------------------------------------------------------------------------- +# full vcs+gcc opts +#---------------------------------------------------------------------------------------- +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) ######################################################################################### # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + -debug_pp $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + +define+DEBUG \ + -debug_pp ######################################################################################### # create a vcs vpd rule @@ -60,9 +138,26 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### -# general cleanup rule +# general cleanup rules ######################################################################################### -.PHONY: clean +.PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf csrc/ $(sim) ucli.key vc_hdrs.h + +clean-sim-debug: + rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h + +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..07ece1c5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -22,7 +22,7 @@ include $(base_dir)/variables.mk sim_name = verilator ######################################################################################### -# vcs simulator types and rules +# verilator simulator types and rules ######################################################################################### sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) @@ -47,67 +47,141 @@ debug: $(sim_debug) include $(base_dir)/common.mk ######################################################################################### -# verilator binary and flags +# verilator-specific user-interface variables and commands +######################################################################################### +HELP_COMPILATION_VARIABLES += \ +" VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \ +" 'all' if full verilator runtime profiling" \ +" 'threads' if runtime thread profiling only" \ +" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" + +HELP_COMMANDS += \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and verilator-generated files" \ +" clean-sim-debug = removes debug simulator and verilator-generated files" + +######################################################################################### +# verilator/cxx binary and flags ######################################################################################### VERILATOR := verilator --cc --exe -CXXFLAGS := \ - $(CXXFLAGS) -O1 -std=c++11 \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -D__STDC_FORMAT_MACROS \ - $(EXTRA_SIM_CC_FLAGS) +#---------------------------------------------------------------------------------------- +# user configs +#---------------------------------------------------------------------------------------- +VERILATOR_PROFILE ?= none +RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,) +RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ + --prof-threads --prof-cfuncs,\ + $(if $(filter $(VERILATOR_PROFILE),threads),\ + --prof-threads,)) -LDFLAGS := \ - $(LDFLAGS) \ - -L$(sim_dir) \ - -lpthread +VERILATOR_FST_MODE ?= 0 +TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ + --trace,--trace-fst --trace-threads 1) +TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) -VERILATOR_CC_OPTS = \ +#---------------------------------------------------------------------------------------- +# verilation configuration/optimization +#---------------------------------------------------------------------------------------- +# we initially had --noassert for performance, but several modules use +# assertions, including dramsim, so we enable --assert by default +VMODE := \ -O3 \ - -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ - -LDFLAGS "$(LDFLAGS)" \ - $(RISCV)/lib/libfesvr.a \ - $(dramsim_lib) + --x-assign fast \ + --x-initial fast \ + --assert \ + --output-split 10000 \ + --output-split-cfuncs 10000 -# default flags added for ariane -ARIANE_VERILATOR_FLAGS = \ +# default flags added for ariane (-Wno-fatal needed for -Wall to not cause +# a crash, since 1000s of warnings are generated) +VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ -Wno-UNUSED \ -Wno-UNOPTFLAT \ -Wno-BLKANDNBLK \ - -Wno-style \ - -Wall + -Wno-fatal -# normal flags used for chipyard builds (that are incompatible with ariane) -CHIPYARD_VERILATOR_FLAGS = \ - --assert +# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) +CHIPYARD_VERILATOR_FLAGS := + +# options dependent on whether ariane/NVDLA or chipyard is used +# NOTE: defer the evaluation of this until it is used! +PLATFORM_OPTS = $(shell \ + if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ + then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ + else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) # Use --timescale to approximate timescale behavior of pre-4.034 TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }') -VERILATOR_NONCC_OPTS = \ - $(TIMESCALE_OPTS) \ - --top-module $(VLOG_MODEL) \ - --vpi \ - -Wno-fatal \ - $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ - --output-split 10000 \ - --output-split-cfuncs 100 \ - --max-num-width 1048576 \ - -f $(sim_common_files) \ - $(sim_vsrcs) -VERILATOR_DEFINES = \ +# see: https://github.com/ucb-bar/riscv-mini/issues/31 +MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }') + +PREPROC_DEFINES := \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES) +VERILATOR_NONCC_OPTS = \ + $(RUNTIME_PROFILING_VFLAGS) \ + $(VMODE) \ + $(PLATFORM_OPTS) \ + $(TIMESCALE_OPTS) \ + $(MAX_WIDTH_OPTS) \ + $(PREPROC_DEFINES) \ + --top-module $(VLOG_MODEL) \ + --vpi \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VERILATOR_CXXFLAGS = \ + $(CXXFLAGS) \ + $(RUNTIME_PROFILING_CFLAGS) \ + $(TRACING_CFLAGS) \ + $(CMODE) \ + -std=c++11 \ + -D__STDC_FORMAT_MACROS \ + -DTEST_HARNESS=V$(VLOG_MODEL) \ + -DVERILATOR \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -I$(build_dir) \ + -include $(build_dir)/$(long_name).plusArgs \ + -include $(build_dir)/verilator.h \ + $(EXTRA_SIM_CXXFLAGS) + +VERILATOR_LDFLAGS = \ + $(LDFLAGS) \ + $(RUNTIME_PROFILING_CFLAGS) \ + $(CMODE) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -lpthread \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VERILATOR_CC_OPTS = \ + -CFLAGS "$(VERILATOR_CXXFLAGS)" \ + -LDFLAGS "$(VERILATOR_LDFLAGS)" + +#---------------------------------------------------------------------------------------- +# full verilator+gcc opts +#---------------------------------------------------------------------------------------- +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) ######################################################################################### # verilator build paths and file names @@ -127,13 +201,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir) mkdir -p $(model_dir) - $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### @@ -155,8 +229,21 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### -# general cleanup rule +# general cleanup rules ######################################################################################### -.PHONY: clean +.PHONY: clean clean-sim clean-sim-debug clean: rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf $(model_dir) $(sim) + +clean-sim-debug: + rm -rf $(model_dir_debug) $(sim_debug) + +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk index 067faa2f..4ac17764 100644 --- a/tools/dromajo/dromajo.mk +++ b/tools/dromajo/dromajo.mk @@ -49,7 +49,8 @@ ifdef ENABLE_DROMAJO EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) # CC flags needed for all simulations -EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR) +EXTRA_SIM_CFLAGS += -I$(DROMAJO_DIR) +EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR) # sourced needed for simulation EXTRA_SIM_SOURCES += $(DROMAJO_LIB) diff --git a/variables.mk b/variables.mk index d7eccb49..e41648d4 100644 --- a/variables.mk +++ b/variables.mk @@ -1,23 +1,45 @@ ######################################################################################### # makefile variables shared across multiple makefiles +# - to use the help text, your Makefile should have a 'help' target that just +# prints all the HELP_LINES ######################################################################################### +HELP_COMPILATION_VARIABLES = +HELP_PROJECT_VARIABLES = \ +" SUB_PROJECT = use the specific subproject default variables [$(SUB_PROJECT)]" \ +" SBT_PROJECT = the SBT project that you should find the classes/packages in [$(SBT_PROJECT)]" \ +" MODEL = the top level module of the project in Chisel (normally the harness) [$(MODEL)]" \ +" VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) [$(VLOG_MODEL)]" \ +" MODEL_PACKAGE = the scala package to find the MODEL in [$(MODEL_PACKAGE)]" \ +" CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \ +" CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \ +" GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \ +" TB = wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ +" TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" -######################################################################################### -# variables to invoke the generator -# descriptions: -# SBT_PROJECT = the SBT project that you should find the classes/packages in -# MODEL = the top level module of the project in Chisel (normally the harness) -# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) -# MODEL_PACKAGE = the scala package to find the MODEL in -# CONFIG = the configuration class to give the parameters for the project -# CONFIG_PACKAGE = the scala package to find the CONFIG class -# GENERATOR_PACKAGE = the scala package to find the Generator class in -# TB = wrapper over the TestHarness needed to simulate in a verilog simulator -# TOP = top level module of the project (normally the module instantiated by the harness) -# -# project specific: -# SUB_PROJECT = use the specific subproject default variables -######################################################################################### +HELP_SIMULATION_VARIABLES = \ +" BINARY = riscv binary that the simulator will run" \ +" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" + +HELP_COMMANDS = \ +" help = display this help" + +HELP_LINES = "" \ + " design specifier variables:" \ + " ---------------------------" \ + $(HELP_PROJECT_VARIABLES) \ + "" \ + " compilation variables:" \ + " ----------------------" \ + $(HELP_COMPILATION_VARIABLES) \ + "" \ + " simulation variables:" \ + " ---------------------" \ + $(HELP_SIMULATION_VARIABLES) \ + "" \ + " some useful general commands:" \ + " -----------------" \ + $(HELP_COMMANDS) \ + "" ######################################################################################### # subproject overrides @@ -140,15 +162,15 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # 1) the sed removes a leading {file:} that sometimes needs to be # provided to SBT when a project but not for bloop. # 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the +# destined for the scala Main, however a bug in Bloop's argument parsing causes the # --nailgun-port argument to be lost in this case. Workaround this by prefixing # every main-destined argument with "--args" define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) + cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From d82e7dbed5d46acce92e029d925875ebe8eaddbf Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 10:40:45 -0700 Subject: [PATCH 03/23] Cleanup more --- docs/Simulation/Software-RTL-Simulation.rst | 28 +++++++++++++++++++++ sims/vcs/Makefile | 9 +------ variables.mk | 6 ++--- 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index ca852d36..9219f5a3 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -61,6 +61,11 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. + +.. code-block:: shell + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -141,6 +146,29 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. +Fast Memory Loading +------------------- + +The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + +The ``.hex`` file should be a text file with a hexadecimal number on each line. + +.. code-block:: text + + deadbeef + 0123 + +Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. + +A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. + +.. code-block:: shell + + make run-binary-hex BINARY=test.riscv Generating Waveforms ----------------------- diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 46b3a267..766350ff 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,10 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +include $(base_dir)/vcs.mk .PHONY: default debug default: $(sim) @@ -138,10 +135,6 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) -$(output_dir)/none.vpd: $(sim_debug) - mkdir -p $(output_dir) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) - ######################################################################################### # general cleanup rules ######################################################################################### diff --git a/variables.mk b/variables.mk index e41648d4..e347ccf0 100644 --- a/variables.mk +++ b/variables.mk @@ -162,15 +162,15 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # 1) the sed removes a leading {file:} that sometimes needs to be # provided to SBT when a project but not for bloop. # 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the +# destined for the scala Main, however a bug in Bloop's argument parsing causes the # --nailgun-port argument to be lost in this case. Workaround this by prefixing # every main-destined argument with "--args" define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) + cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif From c3749ce88f5f498fb0b9e19703ae2664aa4a8492 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 10:41:35 -0700 Subject: [PATCH 04/23] Add space --- docs/Simulation/Software-RTL-Simulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 9219f5a3..af568ef4 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -64,6 +64,7 @@ For instance, to run one of the riscv-tools assembly tests. The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. .. code-block:: shell + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. From 4e7b9d195fef6c036469281891403af6bfb7f4da Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 10:45:11 -0700 Subject: [PATCH 05/23] Dedup default simulation rules --- sims/vcs/Makefile | 11 ----------- sims/verilator/Makefile | 7 ------- variables.mk | 8 +++++++- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 766350ff..3f0c0792 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -36,17 +36,6 @@ debug: $(sim_debug) ######################################################################################### include $(base_dir)/common.mk -######################################################################################### -# verilator-specific user-interface variables and commands -######################################################################################### -HELP_COMPILATION_VARIABLES += -HELP_COMMANDS += \ -" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ -" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ -" clean = remove all debug/non-debug simulators and intermediate files" \ -" clean-sim = removes non-debug simulator and verilator-generated files" \ -" clean-sim-debug = removes debug simulator and verilator-generated files" - ######################################################################################### # vcs binary and arguments ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 07ece1c5..e2f85495 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -55,13 +55,6 @@ HELP_COMPILATION_VARIABLES += \ " 'threads' if runtime thread profiling only" \ " VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" -HELP_COMMANDS += \ -" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ -" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ -" clean = remove all debug/non-debug simulators and intermediate files" \ -" clean-sim = removes non-debug simulator and verilator-generated files" \ -" clean-sim-debug = removes debug simulator and verilator-generated files" - ######################################################################################### # verilator/cxx binary and flags ######################################################################################### diff --git a/variables.mk b/variables.mk index e347ccf0..1522aa2e 100644 --- a/variables.mk +++ b/variables.mk @@ -20,8 +20,14 @@ HELP_SIMULATION_VARIABLES = \ " BINARY = riscv binary that the simulator will run" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" +# include default simulation rules HELP_COMMANDS = \ -" help = display this help" +" help = display this help" \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and simulator-generated files" \ +" clean-sim-debug = removes debug simulator and simulator-generated files" HELP_LINES = "" \ " design specifier variables:" \ From 3b991f3ed7c27b2d6b98fdf14ba8521263719e88 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 11:14:01 -0700 Subject: [PATCH 06/23] Move vcs flags to vcs.mk | Misc. cleanup --- common.mk | 2 -- sims/vcs/Makefile | 70 ++-------------------------------------- sims/verilator/Makefile | 1 - tools/dromajo/dromajo.mk | 1 - vcs.mk | 38 ++++++++++++++++++---- vlsi/Makefile | 10 ++++-- 6 files changed, 42 insertions(+), 80 deletions(-) diff --git a/common.mk b/common.mk index 87d4047c..be787a9d 100644 --- a/common.mk +++ b/common.mk @@ -14,7 +14,6 @@ endif ######################################################################################### HELP_COMPILATION_VARIABLES += \ " EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ -" EXTRA_SIM_CFLAGS = CFLAGS for building simulators" \ " EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ " EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ @@ -22,7 +21,6 @@ HELP_COMPILATION_VARIABLES += \ EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= -EXTRA_SIM_CFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 3f0c0792..efe0dc3c 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -41,81 +41,17 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -PREPROC_DEFINES = \ - +define+VCS \ - +define+CLOCK_PERIOD=1.0 \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN - -VCS_NONCC_OPTS = \ - -notice \ - -line \ - +lint=all,noVCDE,noONGS,noUI \ - -timescale=1ns/1ps \ - -quiet \ - -q \ - +rad \ - +vcs+lic+wait \ - +vc+list \ - -error=noZMMCM \ - -error=PCWM-L \ - -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ - +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ - +incdir+$(build_dir) \ - $(PREPROC_DEFINES) \ - -f $(sim_common_files) \ - $(sim_vsrcs) - -#---------------------------------------------------------------------------------------- -# gcc configuration/optimization -#---------------------------------------------------------------------------------------- -# -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 -fbranch-probabilities -march=native - -VCS_CXXFLAGS = \ - $(CXXFLAGS) \ - $(CMODE) \ - -I$(VCS_HOME)/include \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -std=c++11 \ - $(EXTRA_SIM_CXXFLAGS) - -VCS_LDFLAGS = \ - $(LDFLAGS) \ - $(CMODE) \ - -L$(RISCV)/lib \ - -Wl,-rpath,$(RISCV)/lib \ - -L$(sim_dir) \ - -L$(dramsim_dir) \ - -lfesvr \ - -ldramsim \ - $(EXTRA_SIM_LDFLAGS) - -VCS_CC_OPTS = \ - -CFLAGS "$(VCS_CXXFLAGS)" \ - -LDFLAGS "$(VCS_LDFLAGS)" - -#---------------------------------------------------------------------------------------- -# full vcs+gcc opts -#---------------------------------------------------------------------------------------- -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) ######################################################################################### # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ - -debug_pp + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ - +define+DEBUG \ - -debug_pp + +define+DEBUG ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index e2f85495..2cba66ab 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -157,7 +157,6 @@ VERILATOR_CXXFLAGS = \ VERILATOR_LDFLAGS = \ $(LDFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ - $(CMODE) \ -L$(RISCV)/lib \ -Wl,-rpath,$(RISCV)/lib \ -L$(sim_dir) \ diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk index 4ac17764..2069b394 100644 --- a/tools/dromajo/dromajo.mk +++ b/tools/dromajo/dromajo.mk @@ -49,7 +49,6 @@ ifdef ENABLE_DROMAJO EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) # CC flags needed for all simulations -EXTRA_SIM_CFLAGS += -I$(DROMAJO_DIR) EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR) # sourced needed for simulation diff --git a/vcs.mk b/vcs.mk index 93e75c19..28ed0f51 100644 --- a/vcs.mk +++ b/vcs.mk @@ -17,9 +17,37 @@ VCS_CC_OPTS = \ -CC "-std=c++11" \ -CC "$(EXTRA_SIM_CC_FLAGS)" +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VCS_CXXFLAGS = \ + $(CXXFLAGS) \ + $(CMODE) \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -std=c++11 \ + $(EXTRA_SIM_CXXFLAGS) + +VCS_LDFLAGS = \ + $(LDFLAGS) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VCS_CC_OPTS = \ + -CFLAGS "$(VCS_CXXFLAGS)" \ + -LDFLAGS "$(VCS_LDFLAGS)" + VCS_NONCC_OPTS = \ - $(dramsim_lib) \ - $(RISCV)/lib/libfesvr.a \ + -notice \ + -line \ +lint=all,noVCDE,noONGS,noUI \ -error=PCWM-L \ -error=noZMMCM \ @@ -27,7 +55,6 @@ VCS_NONCC_OPTS = \ -quiet \ -q \ +rad \ - +v2k \ +vcs+lic+wait \ +vc+list \ -f $(sim_common_files) \ @@ -35,10 +62,9 @@ VCS_NONCC_OPTS = \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ +incdir+$(build_dir) \ - $(sim_vsrcs) \ - +libext+.v + $(sim_vsrcs) -VCS_DEFINE_OPTS = \ +PREPROC_DEFINES = \ +define+VCS \ +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ +define+RESET_DELAY=$(RESET_DELAY) \ diff --git a/vlsi/Makefile b/vlsi/Makefile index a9e3d3a5..3bbca7e0 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -115,12 +115,16 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " options_meta: 'append'" >> $@ echo " defines:" >> $@ - for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \ + for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ echo ' - "'$$x'"' >> $@; \ done echo " defines_meta: 'append'" >> $@ - echo " compiler_opts:" >> $@ - for x in $(filter-out "",$(filter-out -CC,$(VCS_CC_OPTS))); do \ + echo " compiler_cc_opts:" >> $@ + for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " compiler_ld_opts:" >> $@ + for x in $(filter-out "",$(VCS_LDFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done echo " compiler_opts_meta: 'append'" >> $@ From 15f508bcbf9b5dda5de5db74bf0319a31221defd Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 11:36:48 -0700 Subject: [PATCH 07/23] First pass at updating hammer submodules --- vcs.mk | 6 ------ vlsi/hammer | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/vcs.mk b/vcs.mk index 28ed0f51..9367cca9 100644 --- a/vcs.mk +++ b/vcs.mk @@ -11,12 +11,6 @@ endif CLOCK_PERIOD ?= 1.0 RESET_DELAY ?= 777.7 -VCS_CC_OPTS = \ - -CC "-I$(RISCV)/include" \ - -CC "-I$(dramsim_dir)" \ - -CC "-std=c++11" \ - -CC "$(EXTRA_SIM_CC_FLAGS)" - #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- diff --git a/vlsi/hammer b/vlsi/hammer index cbc907df..56739c32 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit cbc907dfe8005a8d72f1b2fb7b414ad9dbfe14b1 +Subproject commit 56739c32a81c82bdb065613cc3aa878f1ca40d4c diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index e5ec0da8..bd0e5c90 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit e5ec0da8ad471b075de62989001b282e537416d0 +Subproject commit bd0e5c90126cb517928082517cf9af24ec27bfbb From 8743f3ab95ca65d96f9482949a2dcb8fbd04523e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 18 Aug 2020 11:43:40 -0700 Subject: [PATCH 08/23] Bump hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 56739c32..da9c84f3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 56739c32a81c82bdb065613cc3aa878f1ca40d4c +Subproject commit da9c84f35c1b2df0feaba11395ba4e4570ab5b67 From 9bc9d48fe467c67fbd558b413a022c50031605f9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 18 Aug 2020 21:23:13 -0700 Subject: [PATCH 09/23] Fix vlsi/Makefile opts meta --- vlsi/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 3bbca7e0..fe63c346 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -123,11 +123,12 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done + echo " compiler_cc_opts_meta: 'append'" >> $@ echo " compiler_ld_opts:" >> $@ for x in $(filter-out "",$(VCS_LDFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done - echo " compiler_opts_meta: 'append'" >> $@ + echo " compiler_ls_opts_meta: 'append'" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags:" >> $@ From d020058d1994df92e853064b1fa8c7bfa2a04c90 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 18 Aug 2020 23:35:03 -0700 Subject: [PATCH 10/23] Split up LDFLAGS into LDFLAGS and -l --- vcs.mk | 4 +++- vlsi/hammer-synopsys-plugins | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/vcs.mk b/vcs.mk index 9367cca9..daed8af4 100644 --- a/vcs.mk +++ b/vcs.mk @@ -35,9 +35,11 @@ VCS_LDFLAGS = \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) +# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate) VCS_CC_OPTS = \ -CFLAGS "$(VCS_CXXFLAGS)" \ - -LDFLAGS "$(VCS_LDFLAGS)" + -LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \ + $(filter -l%,$(VCS_LDFLAGS)) VCS_NONCC_OPTS = \ -notice \ diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index bd0e5c90..706e3f6e 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit bd0e5c90126cb517928082517cf9af24ec27bfbb +Subproject commit 706e3f6e8dbba8f2e36b009daaf6cf9596ab68e9 From d4af9e16600a67cfeb5c18b464968651ab63f432 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 10:48:43 -0700 Subject: [PATCH 11/23] Fix separator --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 1522aa2e..be022e12 100644 --- a/variables.mk +++ b/variables.mk @@ -43,7 +43,7 @@ HELP_LINES = "" \ $(HELP_SIMULATION_VARIABLES) \ "" \ " some useful general commands:" \ - " -----------------" \ + " -----------------------------" \ $(HELP_COMMANDS) \ "" From de4e311dd341080202b43254750075abbe1a1dd6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 11:21:35 -0700 Subject: [PATCH 12/23] Remove extra CMODE flags --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 2cba66ab..f71f9de5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -136,7 +136,7 @@ VERILATOR_NONCC_OPTS = \ # gcc configuration/optimization #---------------------------------------------------------------------------------------- # -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 -fbranch-probabilities -march=native +CMODE := -O3 VERILATOR_CXXFLAGS = \ $(CXXFLAGS) \ From 0dd2197477a1e578925dcb2bebd7f65b7bdf39f4 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 21:48:19 -0700 Subject: [PATCH 13/23] Fix meta key --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index fe63c346..c0a6fdd3 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -128,7 +128,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file for x in $(filter-out "",$(VCS_LDFLAGS)); do \ echo ' - "'$$x'"' >> $@; \ done - echo " compiler_ls_opts_meta: 'append'" >> $@ + echo " compiler_ld_opts_meta: 'append'" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags:" >> $@ From b7d9472b4ad6a6ba3ad85b3845de812e1be3cfe7 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:10:18 -0700 Subject: [PATCH 14/23] Cleanup help commands --- common.mk | 22 +++++++++++++++------- sims/vcs/Makefile | 7 ------- sims/verilator/Makefile | 7 ------- variables.mk | 2 +- 4 files changed, 16 insertions(+), 22 deletions(-) diff --git a/common.mk b/common.mk index be787a9d..83b74287 100644 --- a/common.mk +++ b/common.mk @@ -13,11 +13,11 @@ endif # specify user-interface variables ######################################################################################### HELP_COMPILATION_VARIABLES += \ -" EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ -" EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ -" EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ -" EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = requirements to build the simulator" +" EXTRA_GENERATOR_REQS = additional make requirements needed for the main generator" \ +" EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = additional make requirements to build the simulator" EXTRA_GENERATOR_REQS ?= EXTRA_SIM_CXXFLAGS ?= @@ -27,7 +27,7 @@ EXTRA_SIM_REQS ?= #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ -" EXTRA_SIM_FLAGS = runtime simulation flags (passed within +permissive)" +" EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" EXTRA_SIM_FLAGS ?= @@ -36,7 +36,8 @@ HELP_COMMANDS += \ " run-binary = run [./$(shell basename $(sim))] and log instructions to file" \ " run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ " run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ -" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" +" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \ +" run-tests = run all assembly and benchmark tests" ######################################################################################### # include additional subproject make fragments @@ -232,6 +233,13 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done + ######################################################################################### # Implicit rule handling ######################################################################################### diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index efe0dc3c..ac792e63 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -72,10 +72,3 @@ clean-sim: clean-sim-debug: rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h - -######################################################################################### -# print help text -######################################################################################### -.PHONY: help -help: - @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index f71f9de5..9965001d 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -232,10 +232,3 @@ clean-sim: clean-sim-debug: rm -rf $(model_dir_debug) $(sim_debug) - -######################################################################################### -# print help text -######################################################################################### -.PHONY: help -help: - @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/variables.mk b/variables.mk index be022e12..7f3d1eee 100644 --- a/variables.mk +++ b/variables.mk @@ -17,7 +17,7 @@ HELP_PROJECT_VARIABLES = \ " TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" HELP_SIMULATION_VARIABLES = \ -" BINARY = riscv binary that the simulator will run" \ +" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" # include default simulation rules From af61c533dab801301d00eb8afd7ebf064b64b156 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:15:55 -0700 Subject: [PATCH 15/23] Merge .PHONY variables --- common.mk | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 83b74287..4aa0a903 100644 --- a/common.mk +++ b/common.mk @@ -161,9 +161,7 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-binary-fast -.PHONY: run-binary-debug -.PHONY: run-fast +.PHONY: run-binary run-binary-fast run-binary-debug run-fast # run normal binary with hardware-logged insn dissassembly run-binary: $(output_dir) $(sim) From 4f3319dc010304c74078dead4f87d5b7b653c6cc Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 19 Aug 2020 22:16:45 -0700 Subject: [PATCH 16/23] Revert make clean for VCS --- sims/vcs/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index ac792e63..a2896380 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -65,7 +65,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) $(sim_prefix)-* + rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h clean-sim: rm -rf csrc/ $(sim) ucli.key vc_hdrs.h From e5158cbe4c4d9fd7554961a1e26291a08eb4e58b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 22:32:47 -0700 Subject: [PATCH 17/23] Rename some variables --- sims/verilator/Makefile | 10 ++++++---- vcs.mk | 4 ++-- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9965001d..52c78eb6 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -80,7 +80,7 @@ TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) #---------------------------------------------------------------------------------------- # we initially had --noassert for performance, but several modules use # assertions, including dramsim, so we enable --assert by default -VMODE := \ +VERILATOR_OPT_FLAGS := \ -O3 \ --x-assign fast \ --x-initial fast \ @@ -92,6 +92,8 @@ VMODE := \ # a crash, since 1000s of warnings are generated) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ + -Werror-PINMISSING \ + -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ @@ -122,7 +124,7 @@ PREPROC_DEFINES := \ VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ - $(VMODE) \ + $(VERILATOR_OPT_FLAGS) \ $(PLATFORM_OPTS) \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ @@ -136,13 +138,13 @@ VERILATOR_NONCC_OPTS = \ # gcc configuration/optimization #---------------------------------------------------------------------------------------- # -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 +CXX_OPT_FLAGS := -O3 VERILATOR_CXXFLAGS = \ $(CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ $(TRACING_CFLAGS) \ - $(CMODE) \ + $(CXX_OPT_FLAGS) \ -std=c++11 \ -D__STDC_FORMAT_MACROS \ -DTEST_HARNESS=V$(VLOG_MODEL) \ diff --git a/vcs.mk b/vcs.mk index daed8af4..ef5761df 100644 --- a/vcs.mk +++ b/vcs.mk @@ -15,11 +15,11 @@ RESET_DELAY ?= 777.7 # gcc configuration/optimization #---------------------------------------------------------------------------------------- # -flto slows down compilation on small-memory and breaks on firesim-manager -CMODE := -O3 -fbranch-probabilities -march=native +CXX_OPT_FLAGS := -O3 -fbranch-probabilities -march=native VCS_CXXFLAGS = \ $(CXXFLAGS) \ - $(CMODE) \ + $(CXX_OPT_FLAGS) \ -I$(RISCV)/include \ -I$(dramsim_dir) \ -std=c++11 \ From 9087b58cf08c722902c9c10d139f3f6db8f01db3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 22:35:02 -0700 Subject: [PATCH 18/23] Add testbench to description --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 7f3d1eee..b187a23d 100644 --- a/variables.mk +++ b/variables.mk @@ -13,7 +13,7 @@ HELP_PROJECT_VARIABLES = \ " CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \ " CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \ " GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \ -" TB = wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ +" TB = testbench wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ " TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" HELP_SIMULATION_VARIABLES = \ From e77e610ee4920873b44398fb32e09dddcf30ebca Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Aug 2020 23:42:41 -0700 Subject: [PATCH 19/23] Fix Hammer Sim --- vcs.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vcs.mk b/vcs.mk index ef5761df..a282aa44 100644 --- a/vcs.mk +++ b/vcs.mk @@ -14,8 +14,7 @@ RESET_DELAY ?= 777.7 #---------------------------------------------------------------------------------------- # gcc configuration/optimization #---------------------------------------------------------------------------------------- -# -flto slows down compilation on small-memory and breaks on firesim-manager -CXX_OPT_FLAGS := -O3 -fbranch-probabilities -march=native +CXX_OPT_FLAGS := -O3 VCS_CXXFLAGS = \ $(CXXFLAGS) \ From 9d3c14034dac9daa763ff9cad82326624d3ae5fb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 10:40:21 -0700 Subject: [PATCH 20/23] Revert Verilator external IP flags --- sims/verilator/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 52c78eb6..685b7939 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -88,8 +88,7 @@ VERILATOR_OPT_FLAGS := \ --output-split 10000 \ --output-split-cfuncs 10000 -# default flags added for ariane (-Wno-fatal needed for -Wall to not cause -# a crash, since 1000s of warnings are generated) +# default flags added for external IP (ariane/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ -Werror-PINMISSING \ @@ -100,12 +99,13 @@ VERILOG_IP_VERILATOR_FLAGS := \ -Wno-UNUSED \ -Wno-UNOPTFLAT \ -Wno-BLKANDNBLK \ - -Wno-fatal + -Wno-style \ + -Wall # normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) CHIPYARD_VERILATOR_FLAGS := -# options dependent on whether ariane/NVDLA or chipyard is used +# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ From 435bfac45e6fa073923eca003cb9e8236074ad2f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 16:10:14 -0700 Subject: [PATCH 21/23] Fix NVDLA/Ariane builds --- sims/verilator/Makefile | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 685b7939..10b28cb7 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -84,15 +84,12 @@ VERILATOR_OPT_FLAGS := \ -O3 \ --x-assign fast \ --x-initial fast \ - --assert \ --output-split 10000 \ --output-split-cfuncs 10000 # default flags added for external IP (ariane/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ @@ -102,8 +99,9 @@ VERILOG_IP_VERILATOR_FLAGS := \ -Wno-style \ -Wall -# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) -CHIPYARD_VERILATOR_FLAGS := +# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA) +CHIPYARD_VERILATOR_FLAGS := \ + --assert # options dependent on whether external IP (ariane/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! @@ -126,6 +124,7 @@ VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ $(VERILATOR_OPT_FLAGS) \ $(PLATFORM_OPTS) \ + -Wno-fatal \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ $(PREPROC_DEFINES) \ From fdda4cf8f5f6704c6814a2cdb48bfae7ec1b258d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 16:21:39 -0700 Subject: [PATCH 22/23] Update the cfuncs split --- sims/verilator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 10b28cb7..295729b7 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -85,7 +85,7 @@ VERILATOR_OPT_FLAGS := \ --x-assign fast \ --x-initial fast \ --output-split 10000 \ - --output-split-cfuncs 10000 + --output-split-cfuncs 100 # default flags added for external IP (ariane/NVDLA) VERILOG_IP_VERILATOR_FLAGS := \ From 51d8d403be75c87e4cd20f83aac90e487f3caa88 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 20 Aug 2020 23:17:25 -0700 Subject: [PATCH 23/23] bump hammer/hammer-synopsys plugins --- vlsi/hammer | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index da9c84f3..bed4d340 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit da9c84f35c1b2df0feaba11395ba4e4570ab5b67 +Subproject commit bed4d34094fa4c72db37a0066050c475eb5e37b2 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index 706e3f6e..f8a79222 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit 706e3f6e8dbba8f2e36b009daaf6cf9596ab68e9 +Subproject commit f8a7922220c70b6905b37ab30bda6c791b594792