From fec43fc14725859ec144c63f7c9a64f1c95cc512 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Thu, 4 May 2023 21:51:00 -0700 Subject: [PATCH] corner case --- scripts/uniquify-module-names.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 12a0843e..75fc8c85 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -53,7 +53,7 @@ def get_modules_in_verilog_file(file): for line in lines: words = line.split() if len(words) > 0 and words[0] == "module": - module_names.append(words[1].replace("(", "")) + module_names.append(words[1].replace("(", "").replace(")", "").replace(";", "")) return module_names def get_modules_in_filelist(verilog_module_filename, cc_filelist):