Commit Graph

7 Commits

Author SHA1 Message Date
alonamid
2def0dfea7 change dir structure 2019-03-12 14:30:38 -07:00
Paul Rigge
ddf3159d61 Bump rocket, make possible to use published deps (#47)
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
2019-03-06 18:22:21 -08:00
John Wright
acd76e5410 Adding barstools to separate the top from harness and to generate the
memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00
Albert Ou
220aeea4c8 Bump rocket-chip
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
2018-09-29 13:30:07 -07:00
Howard Mao
a3684d01dd use build.sbt instead of jar files to collect packages 2018-05-03 17:09:59 -07:00
Howard Mao
28539dc562 bump rocket-chip to March commit 2018-04-16 19:33:51 -07:00
Howard Mao
7074420aba initial commit 2016-10-21 16:03:26 -07:00