9 Commits

Author	SHA1	Message	Date
abejgonzalez	70d43210d8	[temp] Unable to build/get past chisel-testers	2020-11-15 18:18:04 -08:00
David Biancolin	ce67134329	Support using bloop instead of SBT	2020-06-21 23:25:53 +00:00
David Biancolin	0bdf39ffe4	[SBT] Hush up scalasbt resolver http complaint	2020-05-09 04:21:49 +00:00
David Biancolin	a67461df7a	[SBT] Quiet down jgit http warnings	2020-04-23 16:30:37 -07:00
David Biancolin	b303cf6e81	Rocket Chip Stage/Phase Bump (#503) ... [WIP] Minimally elaborating design Bring up a feature-complete Chipyard stage Pull in Makefrag generation; Bump submodules Update config generation, and global reset scheme Bump submodules; clean up Bump FireSim Remove some unhygenic comments / WS Remove the rocketchip subproject [CI] Lengthen ariane tests timeout Address some remaining reviewer comments [firechip] Refresh a Field that cannot be used across repeated instantiations Bump all submodules	2020-04-18 17:54:27 +00:00
Howard Mao	2eeda43b93	make firrtl-interpreter a submodule instead of depending on external snapshot	2019-09-12 00:19:55 +08:00
abejgonzalez	adb8897e35	add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins	2019-04-17 23:11:14 -07:00
abejgonzalez	7d887b212c	align rebar with tip of project-template master | fixes build issues	2019-04-17 16:02:44 -07:00
John Wright	acd76e5410	Adding barstools to separate the top from harness and to generate the ... memories as external modules, which makes VLSI flows easier to plug in.	2019-02-13 21:13:08 -08:00