Commit Graph

542 Commits

Author SHA1 Message Date
abejgonzalez
5505aef30f Bump sifive-blocks 2021-01-08 10:56:30 -08:00
abejgonzalez
4d3ff26a73 Bump testchipip 2021-01-04 15:36:00 -08:00
abejgonzalez
a6ca3d21ad Bump testchipip 2020-12-28 16:07:57 -08:00
abejgonzalez
b1cedf2d61 Make TinyRocketConfig work with multi-clock work 2020-12-28 09:55:10 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
Tim Snyder
0f47d80edb bump boom along same PR 2020-12-23 15:00:57 +00:00
Tim Snyder
e22350092b bump boom along same PR 2020-12-21 18:27:47 +00:00
Tim Snyder
29ab6301e0 bump sifive-cache for merged sifive/block-inclusivecache-sifive#15
my previous bump duplicated an earlier PR
2020-12-21 18:15:49 +00:00
Tim Snyder
72d084da8f update parameter classes for RC additions 2020-12-18 23:24:19 +00:00
Tim Snyder
a7e6de835a rm *XTypeKey. upstreamed to RC 2020-12-18 23:22:03 +00:00
Tim Snyder
cb558b5952 bump boom along same PR 2020-12-18 23:20:31 +00:00
Tim Snyder
a2ce14f8d3 Bump sodor for ucb-bar/riscv-sodor#60 2020-12-18 21:03:12 +00:00
Tim Snyder
2ce5f6a407 Bump cva6 for ucb-bar/cva6-wrapper#11 2020-12-18 20:54:31 +00:00
Tim Snyder
022dbf976f Bump boom along in the same PR 2020-12-18 20:52:30 +00:00
Tim Snyder
f7a372153a Bump hwacha for ucb-bar/hwacha#24 2020-12-18 20:52:00 +00:00
Tim Snyder
5ff5b4e8b7 Bump sifive-cache for sifive/block-inclusivecache-sifive#18 2020-12-18 20:05:29 +00:00
Tim Snyder
c6dfa1d8c5 Bump testchipip for ucb-bar/testchipip#111 2020-12-18 18:03:51 +00:00
Tim Snyder
95420baccf Bump boom for riscv-boom/riscv-boom#508
non-master pre-merge bump
2020-12-18 18:00:30 +00:00
Tim Snyder
f693972e12 Start RC bump
Bump to pre-merge chipsalliance/rocket-chip#2764 to get it
going while picking up the chisel/firrtl bugfixes in 3/1.4.1+
2020-12-18 18:00:21 +00:00
David Biancolin
1bd51447fe [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2020-12-13 10:45:51 -05:00
David Biancolin
8f1e20936f Update FireSim CI. Push threading into test context 2020-12-12 13:41:32 -08:00
abejgonzalez
98a3e443ce Merge remote-tracking branch 'origin/dev' into local-chisel34 2020-12-11 15:08:02 -08:00
abejgonzalez
fe4aa6cade Bump BOOM/Gemmini 2020-12-11 14:20:09 -08:00
abejgonzalez
5c7c1295a1 Bump Gemmini+Dsptools | Fix SBT_OPTs in CI 2020-12-11 11:37:25 -08:00
abejgonzalez
d4d483c081 Bump BOOM | Use ucb-bar fork chisel-testers 2020-12-11 10:19:02 -08:00
David Biancolin
ee436c9b3f [firechip] Fix a uart multiclock bug 2020-12-10 07:18:12 +00:00
David Biancolin
1787fda8c3 Bump icenet 2020-12-10 06:34:39 +00:00
David Biancolin
76ba68b02f Bump hwacha 2020-12-10 06:34:30 +00:00
abejgonzalez
f1df2ec69e Bump FireSim/Hwacha | Cleanup linting 2020-12-03 12:51:24 -08:00
abejgonzalez
3bc1bdb841 Bump BOOM | Split JAVA/SBT options in CI 2020-12-02 15:49:35 -08:00
abejgonzalez
145885390f Bump Hwacha 2020-12-02 15:08:06 -08:00
Jerry Zhao
70d41996dd Merge pull request #721 from ucb-bar/jerryz123-patch-1
Add config fragment for replacing L2 with broadcastManager
2020-12-02 10:11:12 -08:00
abejgonzalez
b7ed614b19 Attempt at "fixing" build.sbt | Bump sub-projects 2020-11-30 21:22:55 -08:00
abejgonzalez
8a46d4a1ea Bump BOOM and Barstools 2020-11-27 17:34:48 -08:00
abejgonzalez
f1fdab5bd3 Move TL mem switch frag to CY | Add require to not have TL/AXI backing mem 2020-11-23 16:58:34 -08:00
abejgonzalez
8f6de22e72 Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs 2020-11-23 16:30:39 -08:00
Howard Mao
14de80b6e2 Merge pull request #720 from ucb-bar/icenet-tap-fixes
Icenet tap fixes
2020-11-23 19:05:10 -05:00
abejgonzalez
661a7701a7 Share DigitalTop/ChipyardSystem | Fix small naming compile error 2020-11-23 15:46:03 -08:00
Howard Mao
94c85c70bb bump IceNet for input/output tap and checksum fixes 2020-11-23 09:18:11 -08:00
abejgonzalez
571e7517eb Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral 2020-11-19 20:06:28 -08:00
abejgonzalez
5b1b4b3efe Bump Gemmini/Hwacha/Sha3 2020-11-19 15:28:24 -08:00
Jerry Zhao
1b00d540f0 Add config fragment for replacing L2 with broadcastManager 2020-11-17 15:14:30 -08:00
abejgonzalez
70d43210d8 [temp] Unable to build/get past chisel-testers 2020-11-15 18:18:04 -08:00
abejgonzalez
9ea23d43a7 Merge remote-tracking branch 'origin/dev' into local-chisel34 2020-11-15 16:03:25 -08:00
abejgonzalez
d94a8efd43 Fix TLMemPort comment | Use Option instead of NoSimulator 2020-11-15 15:44:38 -08:00
abejgonzalez
63b3d4290f Change NotSimulator to NoSimulator 2020-11-12 15:39:57 -08:00
abejgonzalez
7ca3be236c Bump bringup VCU118 | Ignore HTIF if no-debug module 2020-11-12 11:47:16 -08:00
Tim Snyder
1110dd702c Bump RC, firesim and barstools for chisel3.4 updates
Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).

Requires: ucb-bar/barstools#92 and firesim/firesim#658

The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests.  You will likely want to bump further.
2020-11-11 18:57:16 +00:00
David Biancolin
80487cc371 Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out} 2020-11-10 11:58:53 -08:00
David Biancolin
230bd81e0e [firechip] Update legacy firechip config 2020-11-09 09:26:30 -08:00