Jerry Zhao
b777019c8b
Bump bloop to 1.5.3
2022-09-19 16:43:22 +00:00
David Biancolin and GitHub
171ee8b74a
Add bloop back to sbt plugins. ( #1167 )
2022-05-17 15:25:46 -07:00
David Biancolin and abejgonzalez
6b16d40c41
Aggressively remove SBT plugins that may no longer be needed
2022-01-17 11:16:15 -08:00
David Biancolin
a5b412cfbc
Remove sriracha and generated .sbtopts
2021-12-07 04:58:54 +00:00
abejgonzalez
a0e2dcfc4e
Remove support for bloop
2020-12-02 14:46:46 -08:00
abejgonzalez
b7ed614b19
Attempt at "fixing" build.sbt | Bump sub-projects
2020-11-30 21:22:55 -08:00
abejgonzalez
3dfc03c31d
Add more plugins and libdeps
2020-11-20 17:02:59 -08:00
abejgonzalez
c6e49e0716
Follow RC's SBT sriracha use | Bump FIRRTL plugin
2020-11-20 15:05:00 -08:00
abejgonzalez
a0d479f3ea
Working FIRRTL/RC/Chisel3 build | chisel-testers still broken
2020-11-16 22:55:04 -08:00
abejgonzalez
70d43210d8
[temp] Unable to build/get past chisel-testers
2020-11-15 18:18:04 -08:00
David Biancolin
ce67134329
Support using bloop instead of SBT
2020-06-21 23:25:53 +00:00
David Biancolin
0bdf39ffe4
[SBT] Hush up scalasbt resolver http complaint
2020-05-09 04:21:49 +00:00
David Biancolin
a67461df7a
[SBT] Quiet down jgit http warnings
2020-04-23 16:30:37 -07:00
David Biancolin
b303cf6e81
Rocket Chip Stage/Phase Bump ( #503 )
...
[WIP] Minimally elaborating design
Bring up a feature-complete Chipyard stage
Pull in Makefrag generation; Bump submodules
Update config generation, and global reset scheme
Bump submodules; clean up
Bump FireSim
Remove some unhygenic comments / WS
Remove the rocketchip subproject
[CI] Lengthen ariane tests timeout
Address some remaining reviewer comments
[firechip] Refresh a Field that cannot be used across repeated instantiations
Bump all submodules
2020-04-18 17:54:27 +00:00
Howard Mao
2eeda43b93
make firrtl-interpreter a submodule instead of depending on external snapshot
2019-09-12 00:19:55 +08:00
abejgonzalez
adb8897e35
add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins
2019-04-17 23:11:14 -07:00
abejgonzalez
7d887b212c
align rebar with tip of project-template master | fixes build issues
2019-04-17 16:02:44 -07:00
John Wright and John Wright
acd76e5410
Adding barstools to separate the top from harness and to generate the
...
memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00
Jerry Zhao