12 Commits

Author SHA1 Message Date
Zhongdi LUO
3c9ced31d5 config: reduce Radiance shared memory to 32 KiB 2026-07-13 09:05:36 +00:00
Zhongdi LUO
02d92f6f88 feat: add blackwell synthesis configuration 2026-07-13 00:04:54 +00:00
Zhongdi LUO
fc32e7f59c chore: update radiance pipelined softmax 2026-07-12 02:00:36 +00:00
Zhongdi LUO
71c84f63a5 chore: update radiance fp16 scalar tmem softmax 2026-07-10 13:03:54 +00:00
Zhongdi LUO
55b7fa2007 chore: update radiance fexp support 2026-07-02 07:26:14 +00:00
Zhongdi LUO
bdca34b2cc Update Radiance for scalar TMEM support 2026-06-24 06:25:39 +00:00
Zhongdi LUO
b0a79c26ee Update radiance pre-TMEM-bank baseline 2026-06-21 08:20:52 +00:00
Zhongdi LUO
d764de5115 Update radiance Blackwell SMEM alignment fix 2026-05-27 08:44:49 +00:00
Zhongdi LUO
3cb58af336 Update radiance for 4-lane Blackwell tensor core 2026-05-27 05:55:17 +00:00
87783dc9f6 Track radiance WU architecture updates
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2026-05-27 09:08:16 +08:00
Zhongdi LUO
9206c4452f Update submodules and gitmodules configuration
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2026-05-26 12:58:22 +00:00
5ce98e1491 Update WU architecture integration 2026-05-25 19:26:23 +08:00
4 changed files with 30 additions and 24 deletions

14
.gitmodules vendored
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@@ -87,22 +87,22 @@
url = https://github.com/ucb-bar/libgloss-htif.git
[submodule "toolchains/riscv-tools/riscv-isa-sim"]
path = toolchains/riscv-tools/riscv-isa-sim
url = https://github.com/richardyrh/riscv-isa-sim
url = https://gh-proxy.org/https://github.com/richardyrh/riscv-isa-sim
[submodule "toolchains/riscv-tools/riscv-openocd"]
path = toolchains/riscv-tools/riscv-openocd
url = https://github.com/riscv/riscv-openocd.git
url = https://gh-proxy.org/https://github.com/riscv/riscv-openocd.git
[submodule "toolchains/riscv-tools/riscv-pk"]
path = toolchains/riscv-tools/riscv-pk
url = https://github.com/riscv-software-src/riscv-pk.git
url = https://gh-proxy.org/https://github.com/riscv-software-src/riscv-pk.git
[submodule "toolchains/riscv-tools/riscv-spike-devices"]
path = toolchains/riscv-tools/riscv-spike-devices
url = https://github.com/ucb-bar/spike-devices.git
url = https://gh-proxy.org/https://github.com/ucb-bar/spike-devices.git
[submodule "toolchains/riscv-tools/riscv-tests"]
path = toolchains/riscv-tools/riscv-tests
url = https://github.com/riscv-software-src/riscv-tests.git
url = https://gh-proxy.org/https://github.com/riscv-software-src/riscv-tests.git
[submodule "toolchains/riscv-tools/riscv-tools-feedstock"]
path = toolchains/riscv-tools/riscv-tools-feedstock
url = https://github.com/ucb-bar/riscv-tools-feedstock.git
url = https://gh-proxy.org/https://github.com/ucb-bar/riscv-tools-feedstock.git
[submodule "tools/DRAMSim2"]
path = tools/DRAMSim2
url = https://github.com/firesim/DRAMSim2.git
@@ -159,4 +159,4 @@
url = https://github.com/ucb-bar/compress-acc.git
[submodule "generators/radiance"]
path = generators/radiance
url = https://github.com/ucb-bar/radiance.git
url = https://git.nudt.space/wu-arch/radiance.git

View File

@@ -27,6 +27,7 @@ class VirgoConfig extends RadianceClusterConfig
class VirgoFP16Config extends RadianceFP16ClusterConfig
class VirgoHopperConfig extends Radiance4CFP16ClusterConfig
class VirgoBlackwellConfig extends RadianceBlackwellClusterConfig
class VirgoBlackwellSynConfig extends RadianceBlackwellClusterSynConfig
class VirgoFlashConfig extends RadianceClusterConfig
class VirgoSynConfig extends RadianceClusterSynConfig
class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig
@@ -57,7 +58,7 @@ class RadianceBaseConfig extends Config(
class RadianceFP16ClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 16) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
new radiance.subsystem.WithRadianceCluster(0) ++
@@ -66,7 +67,7 @@ class RadianceFP16ClusterConfig extends Config(
class Radiance8B8WFP16ClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 8, numWords = 8) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 8, numWords = 8) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
new radiance.subsystem.WithRadianceCluster(0) ++
@@ -75,12 +76,12 @@ class Radiance8B8WFP16ClusterConfig extends Config(
class Radiance4CFP16ClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = true, useVxCache = false) ++
// new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16,
// new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 16,
// memType = radiance.subsystem.TwoReadOneWrite,
// serializeUnaligned = radiance.subsystem.CoreSerialized) ++
// NOTE: Hopper Tensor Core does not work with 16-word config due to the
// address alignment requirement
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
new radiance.subsystem.WithRadianceCluster(0) ++
@@ -88,11 +89,12 @@ class Radiance4CFP16ClusterConfig extends Config(
class RadianceBlackwellClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, tensorCoreBlackwell = true, startupAddress = BigInt("80000000", 16), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, tensorCoreBlackwell = true, numTensorWarps = 2, startupAddress = BigInt("80000000", 16), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
new radiance.subsystem.WithRadianceCluster(0) ++
new radiance.subsystem.WithSimtConfig(nWarps = 4, nCoreLanes = 4, nMemLanes = 4, nSrcIds = 32) ++
new RadianceBaseConfig)
class RadianceClusterConfig extends Config(
@@ -100,7 +102,7 @@ class RadianceClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = false, tensorCoreDecoupled = false, useVxCache = false) ++
// new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 256 << 10/*KBytes*/, numBanks = 8, numWords = 8,
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10/*KBytes*/, numBanks = 8, numWords = 8,
// memType = radiance.subsystem.TwoReadOneWrite,
serializeUnaligned = radiance.subsystem.CoreSerialized) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
@@ -133,7 +135,7 @@ class RadianceBigLittleClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 4, accSizeInKB = 16, tileSize = 16) ++
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 32 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
new radiance.subsystem.WithRadianceCluster(0) ++
@@ -151,6 +153,10 @@ class Radiance4CFP16ClusterSynConfig extends Config(
new radiance.subsystem.WithRadianceSimParams(false) ++
new Radiance4CFP16ClusterConfig)
class RadianceBlackwellClusterSynConfig extends Config(
new radiance.subsystem.WithRadianceSimParams(false) ++
new RadianceBlackwellClusterConfig)
class RadianceBigLittleClusterSynConfig extends Config(
new radiance.subsystem.WithRadianceSimParams(false) ++
new RadianceBigLittleClusterConfig)

View File

@@ -104,8 +104,9 @@ get_waveform_flag = +vcdfile=$(1).$(if $(filter $(USE_FST),0),vcd,fst)
#----------------------------------------------------------------------------------------
# we initially had --noassert for performance, but several modules use
# assertions, including dramsim, so we enable --assert by default
VERILATOR_OUTPUT_SPLIT ?= 10000
VERILATOR_OUTPUT_SPLIT_CFUNCS ?= 100
VERILATOR_OUTPUT_SPLIT ?= 2000
VERILATOR_OUTPUT_SPLIT_CFUNCS ?= 20
VERILATOR_OUTPUT_GROUPS ?= 0
VERILATOR_OPT_FLAGS ?= \
-O0 \
@@ -169,6 +170,7 @@ VERILATOR_NONCC_OPTS = \
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
-O0 \
-fno-inline \
-DVERILATOR
@@ -199,25 +201,23 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
# build makefile fragment that builds the verilator sim rules
#########################################################################################
$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir)
mkdir -p $(model_dir)
$(VERILATOR) -j 36 $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
$(VERILATOR) -j $(VERILATOR_MAKE_JOBS) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
touch $@
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
mkdir -p $(model_dir_debug)
$(VERILATOR) -j 36 $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
$(VERILATOR) -j $(VERILATOR_MAKE_JOBS) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
touch $@
#########################################################################################
# invoke make to make verilator sim rules
#########################################################################################
$(sim): $(model_mk) $(dramsim_lib)
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O0 OPT_SLOW=-O0 OPT_GLOBAL=-O0 -C $(model_dir) -f V$(TB).mk
$(sim_debug): $(model_mk_debug) $(dramsim_lib)
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O0 OPT_SLOW=-O0 OPT_GLOBAL=-O0 -C $(model_dir_debug) -f V$(TB).mk
#########################################################################################
# create a verilator vpd rule