20 lines
1.6 KiB
ReStructuredText
20 lines
1.6 KiB
ReStructuredText
Chisel
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===========================
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`Chisel <https://chisel-lang.org/>`__ is an open-source hardware description language embedded in Scala.
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It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
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After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
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First is the compilation step.
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If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions.
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Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more.
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After the compilation is complete, elaboration begins.
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The Chisel generator starts elaboration using the module and configuration classes passed to it.
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This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code.
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If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library".
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However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral!
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See :ref:`Tools/FIRRTL:FIRRTL` for more information on how to get a FIRRTL file to Verilog.
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For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
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Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel-lang.org/>`__.
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