61 lines
2.2 KiB
Tcl
61 lines
2.2 KiB
Tcl
#### Command line arguments to this script
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# argv[0] = absolute path to post_synth checkpoint file
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# argv[1] = part
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# argv[2] = output directory
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# argv[3] = common fpga brand tcl
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set synth_checkpoint_file [lindex $argv 0]
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set board [lindex $argv 1]
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set wrkdir [lindex $argv 2]
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set scriptdir [lindex $argv 3]
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# Set the variable for all the common files
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set commondir [file dirname $scriptdir]
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# Set the variable that points to board specific files
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set boarddir [file join [file dirname $commondir] $board]
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source [file join $boarddir tcl board.tcl]
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# Set the project part to the part passed into this script
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set_part $part_fpga
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# Create output directories if they doesn't exist
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file mkdir $wrkdir
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set rptdir [file join $wrkdir report]
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file mkdir $rptdir
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# Load synthesis checkpoint
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open_checkpoint $synth_checkpoint_file
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# opt
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opt_design
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write_checkpoint -force [file join $wrkdir post_opt]
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# place
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place_design
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phys_opt_design
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write_checkpoint -force [file join $wrkdir post_place]
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report_timing_summary -file [file join $rptdir post_place_timing_summary.rpt]
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report_drc -file [file join $rptdir post_place_drc.rpt]
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# route
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route_design
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write_checkpoint -force [file join $wrkdir post_route]
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report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt]
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report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt]
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report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt]
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report_utilization -file [file join $rptdir post_route_utilization.rpt]
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report_drc -file [file join $rptdir post_route_drc.rpt]
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report_cdc -details -file [file join $rptdir post_route_cdc.rpt]
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report_clock_interaction -file [file join $rptdir post_route_clock_interaction.rpt]
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report_bus_skew -file [file join $rptdir post_route_bus_skew.rpt]
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report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file [file join $rptdir post_route_timing_violations.rpt]
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# bitstream
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write_verilog -force [file join $wrkdir post_route.v]
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write_xdc -no_fixed_only -force [file join $wrkdir post_route.xdc]
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write_bitstream -force [file join $wrkdir top.bit]
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write_debug_probes -force [file join $wrkdir debug_nets.ltx]
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