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chipyard/vlsi/add.mems.conf
Richard Yan ae427a8a2d vlsi changes
2024-09-22 01:15:38 -07:00

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name dcache_data depth 16 width 1024 ports mwrite,read mask_gran 8
name dcache_tags depth 16 width 24 ports write,read
name cache_mshr depth 8 width 305 ports write,read
name icache_data depth 128 width 1024 ports mwrite,read mask_gran 8
name icache_tags depth 128 width 21 ports write,read
name rf_bank depth 64 width 32 ports write,read