13 lines
813 B
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13 lines
813 B
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FIRRTL
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`FIRRTL <https://github.com/freechipsproject/firrtl>`__ is an intermediate representation of your circuit.
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It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog.
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Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which passes the circuit through a series of circuit-level transformations.
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An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
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Once the transformations are done, a Verilog file is emitted and the build process is done.
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To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section.
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For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.
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