59 lines
1.4 KiB
YAML
59 lines
1.4 KiB
YAML
# Override configurations in ../example-sky130.yml and example-designs
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# Specify clock signals
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# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
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vlsi.inputs.clocks: [
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{name: "clock", period: "30ns", uncertainty: "3ns"}
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]
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# Placement Constraints
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "RocketTile"
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type: toplevel
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x: 0
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y: 0
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width: 4000
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height: 3000
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margins:
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left: 10
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right: 0
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top: 10
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bottom: 10
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# Place SRAM memory instances
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- path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 50
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orientation: r90
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- path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 450
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orientation: r90
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- path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 850
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orientation: r90
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- path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 1250
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orientation: r90
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# tag array
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- path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 1600
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orientation: r90
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# instruction cache
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- path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 2100
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orientation: r90
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