91 lines
2.5 KiB
YAML
91 lines
2.5 KiB
YAML
# Override configurations in ../example-sky130.yml
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# Specify clock signals
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# Relax the clock period for OpenROAD to meet timing
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vlsi.inputs.clocks: [
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{name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
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]
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# Flow parameters that yield a routable design with reasonable timing
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par.openroad:
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timing_driven: true # set to false to drastically speed up runs
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create_archive_mode: none
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write_reports: true # set to false to slightly speed up runs
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floorplan_mode: generate
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macro_placement.halo: [50, 50]
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global_placement.timing_driven: true
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global_placement.routability_driven: true
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global_placement.placement_padding: 6
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detailed_placement.placement_padding: 4
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clock_tree.placement_padding: 2
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clock_tree_resize.placement_padding: 0
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clock_tree_resize.setup_margin: 0.0
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clock_tree_resize.hold_margin: 0.20
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global_route_resize.hold_margin: 0.60
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clock_tree_resize.hold_max_buffer_percent: 80
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global_placement.routing_adjustment: 0.5
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global_route.routing_adjustment: 0.3
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global_route_resize.routing_adjustment: 0.2
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# DRC/LVS configuration
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drc.magic.generate_only: true
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lvs.netgen.generate_only: true
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 4000
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height: 3000
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margins:
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left: 10
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right: 0
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top: 10
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bottom: 10
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# Place SRAM memory instances
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 50
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orientation: r90
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 450
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orientation: r90
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 850
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orientation: r90
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 1250
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orientation: r90
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# tag array
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 1600
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orientation: r90
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# instruction cache
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 2100
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orientation: r90
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