1f98c84210
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success). * A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. * BuildTop now builds a ChipTop dut module in the TestHarness by default * A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top) * The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). * IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. * The default for the TOP make variable is now ChipTop (was Top)
105 lines
3.9 KiB
Scala
105 lines
3.9 KiB
Scala
//See LICENSE for license details.
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package firesim.firesim
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import chisel3._
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossing}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.util.{ResetCatchAndSync}
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import boom.common.{BoomTilesKey, BoomCrossingKey}
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import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
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import firesim.configs._
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import chipyard.{BuildSystem, DigitalTop, DigitalTopModule}
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import chipyard.config.ConfigValName._
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import chipyard.iobinders.{IOBinders}
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// WIP! This file is a sketch of one means of defining a multiclock target-design
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// that can be simulated in FireSim, pending a canonicalized form in Chipyard.
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//
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// Note, the main prerequisite for supporting an additional clock domain in a
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// FireSim simulation is to supply an additional clock parameter
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// (RationalClock) to the clock bridge (RationalClockBridge). The bridge
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// produces a vector of clocks, based on the provided parameter list, which you
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// may use freely without further modifications to your target design.
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case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) {
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def numClocks(): Int = additionalClocks.size + 1
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}
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case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq()))
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trait HasAdditionalClocks extends LazyModuleImp {
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val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock())))
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}
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// Presupposes only 1 or 2 clocks.
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trait HasFireSimClockingImp extends HasAdditionalClocks {
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val outer: HasTiles
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val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
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case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
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case None => (clocks.head, reset)
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}
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outer.tiles.foreach({ case tile =>
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tile.module.clock := tileClock
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tile.module.reset := tileReset
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})
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}
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// Config Fragment
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class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => {
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case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
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case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
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r.copy(crossingType = RationalCrossing())
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}
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case BoomCrossingKey => up(BoomCrossingKey, site) map { r =>
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r.copy(crossingType = RationalCrossing())
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}
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})
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class HalfRateUncore extends WithSingleRationalTileDomain(2,1)
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class WithFiresimMulticlockTop extends Config((site, here, up) => {
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case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module)
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})
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// Complete Config
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class FireSimQuadRocketMulticlockConfig extends Config(
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new HalfRateUncore ++
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new WithFiresimMulticlockTop ++
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new FireSimQuadRocketConfig)
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// Top Definition
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class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop
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{
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override lazy val module = new FiresimMulticlockTopModule(this)
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}
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class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp
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// Harness Definition
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class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
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val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
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val refClock = clockBridge.io.clocks.head
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val reset = WireInit(false.B)
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withClockAndReset(refClock, reset) {
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// Instantiate multiple instances of the DUT to implement supernode
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val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
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val peekPokeBridge = PeekPokeBridge(refClock, reset)
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// A Seq of partial functions that will instantiate the right bridge only
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// if that Mixin trait is present in the target's class instance
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//
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// Apply each partial function to each DUT instance
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for ((target) <- targets) {
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p(IOBinders).values.map(_(target))
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}
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targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
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}
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}
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