116 lines
3.9 KiB
ReStructuredText
116 lines
3.9 KiB
ReStructuredText
Memory Hierarchy
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===============================
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The L1 Caches
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--------------
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Each CPU tile has an L1 instruction cache and L1 data cache. The size and
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associativity of these caches can be configured. The default ``RocketConfig``
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uses 16 KiB, 4-way set-associative instruction and data caches. However,
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if you use the ``NMediumCores`` or ``NSmallCores`` configurations, you can
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configure 4 KiB direct-mapped caches for L1I and L1D.
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.. code-block:: scala
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import freechips.rocketchip.subsystem.{WithNMediumCores, WithNSmallCores}
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class SmallRocketConfig extends Config(
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new WithNSmallCores(1) ++
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new RocketConfig)
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class MediumRocketConfig extends Config(
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new WithNMediumCores(1) ++
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new RocketConfig)
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You can also configure the L1 data cache as an data scratchpad instead.
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However, there are some limitations on this. If you are using a data scratchpad,
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you can only use a single core and you cannot give the design an external DRAM.
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.. code-block:: scala
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import freechips.rocketchip.subsystem.{WithNoMemPort, WithScratchpadsOnly}
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class ScratchpadRocketConfig extends Config(
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new WithNoMemPort ++
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new WithScratchpadsOnly ++
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new SmallRocketConfig)
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The SiFive L2 Cache
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-------------------
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The default RocketConfig provided in the Chipyard example project uses SiFive's
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InclusiveCache generator to produce a shared L2 cache. In the default
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configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way
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set-associativity. However, you can change these parameters to obtain your
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desired cache configuration. The main restriction is that the number of ways
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and the number of banks must be powers of 2.
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.. code-block:: scala
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import freechips.rocketchip.subsystem.WithInclusiveCache
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# Create an SoC with 1 MB, 4-way, 4-bank cache
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class MyCacheRocketConfig extends Config(
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new WithInclusiveCache(
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capacityKB = 1024,
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nWays = 4,
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nBanks = 4) ++
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new RocketConfig)
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The Broadcast Hub
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-----------------
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If you do not want to use the L2 cache (say, for a resource-limited embedded
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design), you can create a configuration without it. Instead of using the L2
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cache, you will instead use RocketChip's TileLink broadcast hub.
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To make such a configuration, you can just copy the definition of
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``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the
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list of included mixims.
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.. code-block:: scala
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import freechips.rocketchip.subsystem.{WithNBigCores, BaseConfig}
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class CachelessRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new WithNBigCores(1) ++
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new BaseConfig)
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If you want to reduce the resources used even further, you can configure
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the Broadcast Hub to use a bufferless design.
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.. code-block:: scala
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import freechips.rocketchip.subsystem.WithBufferlessBroadcastHub
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class BufferlessRocketConfig extends Config(
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new WithBufferlessBroadcastHub ++
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new CachelessRocketConfig)
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The Outer Memory System
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-----------------------
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The L2 coherence agent (either L2 cache of Broadcast Hub) makes requests to
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an outer memory system consisting of an AXI4-compatible DRAM controller.
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The default configuration uses a single memory channel, but you can configure
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the system to use multiple channels. As with the number of L2 banks, the
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number of DRAM channels is restricted to powers of two.
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.. code-block:: scala
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import freechips.rocketchip.subsystem.WithNMemoryChannels
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class DualChannelRocketConfig extends Config(
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new WithNMemoryChannels(2) ++
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new RocketConfig)
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In VCS and Verilator simulation, the DRAM is simulated using the
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``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each
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memory channel.
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If you want a more realistic memory simulation, you can use FireSim, which
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can simulate the timing of DDR3 controllers. More documentation on FireSim
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memory models is available in the `FireSim docs <https://docs.fires.im/en/latest/>`_.
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