abejgonzalez 244205e2b4 Separate new sys_clk and ddr2 from TSI

2020-11-08 17:49:32 -08:00

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fpga-shells @ 89a5efec01

UART Working... Bumped to newer fpga-shells

2020-10-19 11:29:25 -07:00

scripts

Add BootROM | Fix ResetWrangler for DDR | Add scripts

2020-10-20 21:20:11 -07:00

src/main

Separate new sys_clk and ddr2 from TSI

2020-11-08 17:49:32 -08:00

.gitignore

Add BootROM | Fix ResetWrangler for DDR | Add scripts

2020-10-20 21:20:11 -07:00

Makefile

Fix Arty merge and errors from CY bump

2020-11-05 15:04:44 -08:00