abejgonzalez 1d52899736 Remove GenerateSimFiles and use make instead

2021-05-06 00:27:11 -07:00

..

boom @ e1a70afed7

bump boom along same PR

2020-12-23 15:00:57 +00:00

chipyard/src

Remove GenerateSimFiles and use make instead

2021-05-06 00:27:11 -07:00

cva6 @ 139741a584

Bump cva6 for ucb-bar/cva6-wrapper#11

2020-12-18 20:54:31 +00:00

firechip/src

Update harnessClk/Rst naming to buildtop | Small docs cleanup

2021-03-22 13:11:12 -07:00

gemmini @ 9a92fa07e7

Bump gemmini for config changes

2021-02-25 23:00:39 -08:00

hwacha @ 62c01f5a88

Bump hwacha for ucb-bar/hwacha#24

2020-12-18 20:52:00 +00:00

icenet @ 084ca50706

Bump icenet

2020-12-10 06:34:39 +00:00

nvdla @ b2b78c9f89

NVDLA Integration + Cleanup Ariane Preprocessing (#505)

2020-05-16 12:22:30 -07:00

riscv-sodor @ 449354c27b

Bump testchipip and sodor | increase sodor SerialTL width for faster binary loading

2021-01-10 23:39:16 -08:00

rocket-chip @ a7b016e46e

Start RC bump

2020-12-18 18:00:21 +00:00

sha3 @ 74e41f5792

Attempt at "fixing" build.sbt | Bump sub-projects

2020-11-30 21:22:55 -08:00

sifive-blocks @ 545a396f34

Bump sifive-blocks

2021-01-08 10:56:30 -08:00

sifive-cache @ e3a3000cc1

bump sifive-cache for merged sifive/block-inclusivecache-sifive#15

2020-12-21 18:15:49 +00:00

testchipip @ 0743c5a941

bump testchipip

2021-05-05 03:25:39 +00:00

tracegen

update parameter classes for RC additions

2020-12-18 23:24:19 +00:00