140 lines
3.8 KiB
YAML
140 lines
3.8 KiB
YAML
# Technology Setup
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# Technology used is ASAP7
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vlsi.core.technology: asap7
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# Specify dir with ASAP7 tarball
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technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL"
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vlsi.core.max_threads: 12
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# General Hammer Inputs
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vlsi.inputs.supplies.VDD: "0.7 V"
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# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
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vlsi.inputs.power_spec_mode: "auto"
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vlsi.inputs.power_spec_type: "cpf"
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# Specify the setup and hold corners for ASAP7
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vlsi.inputs.mmmc_corners: [
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{name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"},
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{name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"}
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]
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# Specify clock signals
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vlsi.inputs.clocks: [
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{name: "clock", period: "1ns", uncertainty: "0.1ns"}
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]
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# Generate Make include to aid in flow
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vlsi.core.build_system: make
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# Power Straps
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par.power_straps_mode: generate
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par.generate_power_straps_method: by_tracks
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par.blockage_spacing: 2.0
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par.generate_power_straps_options:
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by_tracks:
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strap_layers:
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- M3
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- M4
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- M5
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- M6
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- M7
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- M8
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- M9
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track_width: 5
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track_spacing: 0
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track_start: 10
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power_utilization: 0.05
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power_utilization_M8: 1.0
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power_utilization_M9: 1.0
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "Sha3AccelwBB"
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type: "toplevel"
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x: 0
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y: 0
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width: 300
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height: 300
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margins:
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left: 0
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right: 0
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top: 0
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bottom: 1.08 #must be at least this number
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- path: "Sha3AccelwBB/dco"
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type: "hardmacro"
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x: 100
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y: 100
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width: 32
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height: 32
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orientation: "r0"
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# Pin placement constraints
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vlsi.inputs.pin_mode: generated
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vlsi.inputs.pin.generate_mode: semi_auto
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vlsi.inputs.pin.assignments: [
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{pins: "*", layers: ["M5", "M7"], side: "bottom"}
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]
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# Paths to extra libraries
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vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
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vlsi.technology.extra_libraries:
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- library:
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nldm liberty file_deepsubst_meta: "local"
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nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib"
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lef file_deepsubst_meta: "local"
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lef file: "extra_libraries/dco/ExampleDCO.lef"
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gds file_deepsubst_meta: "local"
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gds file: "extra_libraries/dco/ExampleDCO.gds"
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corner:
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nmos: "slow"
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pmos: "slow"
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temperature: "100 C"
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supplies:
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VDD: "0.63 V"
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GND: "0 V"
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- library:
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nldm liberty file_deepsubst_meta: "local"
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nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib"
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lef file_deepsubst_meta: "local"
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lef file: "extra_libraries/dco/ExampleDCO.lef"
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gds file_deepsubst_meta: "local"
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gds file: "extra_libraries/dco/ExampleDCO.gds"
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corner:
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nmos: "fast"
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pmos: "fast"
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temperature: "0 C"
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supplies:
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VDD: "0.77 V"
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GND: "0 V"
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# Because the DCO is a dummy layout, we treat it as a physical-only cell
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par.inputs.physical_only_cells_mode: append
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par.inputs.physical_only_cells_list:
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- ExampleDCO
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# SRAM Compiler compiler options
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vlsi.core.sram_generator_tool: "sram_compiler"
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vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]
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vlsi.core.sram_generator_tool_path_meta: "append"
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# Tool options. Replace with your tool plugin of choice.
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# Genus options
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vlsi.core.synthesis_tool: "genus"
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vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
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vlsi.core.synthesis_tool_path_meta: "append"
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synthesis.genus.version: "181"
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# Innovus options
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vlsi.core.par_tool: "innovus"
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vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
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vlsi.core.par_tool_path_meta: "append"
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par.innovus.version: "181"
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par.innovus.design_flow_effort: "standard"
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par.inputs.gds_merge: true
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# Calibre options
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vlsi.core.drc_tool: "calibre"
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vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
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vlsi.core.lvs_tool: "calibre"
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vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
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