40 lines
1.5 KiB
ReStructuredText
40 lines
1.5 KiB
ReStructuredText
.. _checkpointing:
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Architectural Checkpoints
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=========================
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Chipyard supports generating architectural checkpoints using Spike.
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These checkpoints contain a snapshot of the architectural state of a RISC-V SoC at some point in the execution of a program.
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The checkpoints include the contents of cacheable memory, core architectural registers, and core CSRs.
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RTL simulations of SoCs can resume execution from checkpoints after restoring the architectural state.
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.. note::
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Currently, only checkpoints of single-core systems are supported
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Generating Checkpoints
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------------------------
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``scripts/generate-ckpt.sh`` is a script that runs spike with the right commands to generate an architectural checkpoint
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``scripts/generate-ckpt.sh -h`` lists options for checkpoint generation.
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Example: run the ``hello.riscv`` binary for 1000 instructions before generating a checkpoint.
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This should produce a directory named ``hello.riscv.0x80000000.1000.loadarch``
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.. code::
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scripts/generate-ckpt.sh -b tests/hello.riscv -i 1000
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Loading Checkpoints in RTL Simulation
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--------------------------------------
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Checkpoints can be loaded in RTL simulations with the ``LOADARCH`` flag.
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The target config **MUST** use dmi-based bringup (as opposed to the default TSI-based bringup), and support fast ``LOADMEM``.
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The target config should also match the architectural configuration of however spike was configured when generating the checkpoint.
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.. code::
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cd sims/vcs
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make CONFIG=dmiRocketConfig run-binary LOADARCH=../../hello.riscv.0x80000000.1000.loadarch
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