385 lines
17 KiB
Scala
385 lines
17 KiB
Scala
package firesim.firesim
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import java.io.File
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import chisel3._
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import chisel3.util.{log2Up}
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import org.chipsalliance.cde.config.{Parameters, Config}
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import freechips.rocketchip.groundtest.TraceGenParams
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.rocket.DCacheParams
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
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import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.prci.{AsynchronousCrossing}
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import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
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import testchipip.cosim.{TracePortKey, TracePortParams}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import scala.math.{min, max}
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import chipyard.clocking.{ChipyardPRCIControlKey}
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import chipyard.harness.{HarnessClockInstantiatorKey}
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import icenet._
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import firesim.bridges._
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import firesim.configs._
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class WithBootROM extends Config((site, here, up) => {
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case BootROMLocated(x) => {
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val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
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val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
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val bootROMPath = if (chipyardBootROM.exists()) {
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chipyardBootROM.getAbsolutePath()
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} else {
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firesimBootROM.getAbsolutePath()
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}
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up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMPath))
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}
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})
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// Disables clock-gating; doesn't play nice with our FAME-1 pass
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class WithoutClockGating extends Config((site, here, up) => {
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case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
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case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey, site).copy(enableTileClockGating = false)
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})
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// Use the firesim clock bridge instantiator. this is required
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class WithFireSimHarnessClockBridgeInstantiator extends Config((site, here, up) => {
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case HarnessClockInstantiatorKey => () => new FireSimClockBridgeInstantiator
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})
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// Testing configurations
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// This enables printfs used in testing
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class WithScalaTestFeatures extends Config((site, here, up) => {
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case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
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})
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// Multi-cycle regfile for rocket+boom
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class WithFireSimMultiCycleRegfile extends Config((site, here, up) => {
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case FireSimMultiCycleRegFile => true
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})
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// Model multithreading optimization
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class WithFireSimFAME5 extends Config((site, here, up) => {
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case FireSimFAME5 => true
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})
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// FASED Config Aliases. This to enable config generation via "_" concatenation
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// which requires that all config classes be defined in the same package
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class DDR3FCFS extends FCFS16GBQuadRank
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class DDR3FRFCFS extends FRFCFS16GBQuadRank
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class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
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class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
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// Adds a small/large NVDLA to the system
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class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large")
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class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")
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// Minimal set of FireSim-related design tweaks - notably discludes FASED, TraceIO, and the BlockDevice
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class WithMinimalFireSimDesignTweaks extends Config(
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// Required*: Punch all clocks to FireSim's harness clock instantiator
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new WithFireSimHarnessClockBridgeInstantiator ++
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new chipyard.harness.WithHarnessBinderClockFreqMHz(1000.0) ++
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new chipyard.harness.WithClockFromHarness ++
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new chipyard.harness.WithResetFromHarness ++
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new chipyard.config.WithNoClockTap ++
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new chipyard.clocking.WithPassthroughClockGenerator ++
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// Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
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new WithBootROM ++
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// Required: Existing FAME-1 transform cannot handle black-box clock gates
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new WithoutClockGating ++
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// Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
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new WithoutTLMonitors ++
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// Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock)
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new chipyard.config.WithNoDebug
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)
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// Non-frequency tweaks that are generally applied to all firesim configs
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class WithFireSimDesignTweaks extends Config(
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new WithMinimalFireSimDesignTweaks ++
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// Required: Remove the debug clock tap, this breaks compilation of target-level sim in FireSim
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new chipyard.config.WithNoClockTap ++
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// Required: Bake in the default FASED memory model
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new WithDefaultMemModel ++
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// Optional: reduce the width of the Serial TL interface
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new testchipip.serdes.WithSerialTLWidth(4) ++
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// Required*: Scale default baud rate with periphery bus frequency
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new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
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// Optional: Adds IO to attach tracerV bridges
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// new chipyard.config.WithTraceIO ++
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// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
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// Optional: Removing this will require using an initramfs under linux
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new testchipip.iceblk.WithBlockDevice
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)
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// Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
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class WithFireSimHighPerfClocking extends Config(
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// Create clock group for uncore that does not include mbus
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Nil)) ++
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// Optional: This sets the default frequency for all buses in the system to 3.2 GHz
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// (since unspecified bus frequencies will use the pbus frequency)
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// This frequency selection matches FireSim's legacy selection and is required
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// to support 200Gb NIC performance. You may select a smaller value.
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new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
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new chipyard.config.WithControlBusFrequency(3200.0) ++
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new chipyard.config.WithSystemBusFrequency(3200.0) ++
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new chipyard.config.WithFrontBusFrequency(3200.0) ++
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new chipyard.config.WithControlBusFrequency(3200.0) ++
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// Optional: These three configs put the DRAM memory system in it's own clock domain.
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// Removing the first config will result in the FASED timing model running
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// at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.
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// 1 GHz matches the FASED default, using some other frequency will require
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// runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
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new chipyard.config.WithMemoryBusFrequency(1000.0) ++
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new chipyard.config.WithAsynchrousMemoryBusCrossing
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)
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// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
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class WithFireSimConfigTweaks extends Config(
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// 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
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// Using some other frequency will require runnings the FASED runtime configuration generator
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// to generate faithful DDR3 timing values.
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new chipyard.config.WithSystemBusFrequency(1000.0) ++
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new chipyard.config.WithControlBusFrequency(1000.0) ++
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new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
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new chipyard.config.WithControlBusFrequency(1000.0) ++
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new chipyard.config.WithMemoryBusFrequency(1000.0) ++
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new chipyard.config.WithFrontBusFrequency(1000.0) ++
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new WithFireSimDesignTweaks
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)
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// Tweaks to use minimal design tweaks
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// Need to use initramfs to use linux (no block device)
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class WithMinimalFireSimHighPerfConfigTweaks extends Config(
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new WithFireSimHighPerfClocking ++
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new freechips.rocketchip.subsystem.WithNoMemPort ++
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new testchipip.soc.WithMbusScratchpad ++
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new WithMinimalFireSimDesignTweaks
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)
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/**
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* Adds BlockDevice to WithMinimalFireSimHighPerfConfigTweaks
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*/
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class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
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new WithFireSimHighPerfClocking ++
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
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new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
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new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device
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new WithMinimalFireSimDesignTweaks
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)
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/**
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* Adds Block device to WithMinimalFireSimHighPerfConfigTweaks
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*/
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class WithMinimalAndFASEDFireSimHighPerfConfigTweaks extends Config(
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new WithFireSimHighPerfClocking ++
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new WithDefaultMemModel ++ // add default FASED memory model
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new WithMinimalFireSimDesignTweaks
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)
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// Tweaks for legacy FireSim configs.
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class WithFireSimHighPerfConfigTweaks extends Config(
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new WithFireSimHighPerfClocking ++
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new WithFireSimDesignTweaks
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)
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// Tweak more representative of testchip configs
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class WithFireSimTestChipConfigTweaks extends Config(
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// Frequency specifications
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new chipyard.config.WithTileFrequency(1000.0) ++ // Realistic tile frequency for a test chip
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new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency
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new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately
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new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency
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new chipyard.config.WithFrontBusFrequency(500.0) ++ // Match the sbus and fbus frequency
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new chipyard.config.WithControlBusFrequency(500.0) ++ // Match the sbus and cbus frequency
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
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// Crossing specifications
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new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
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new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
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new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
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// new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
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new WithFireSimDesignTweaks
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)
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/*******************************************************************************
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* Full TARGET_CONFIG configurations. These set parameters of the target being
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* simulated.
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*
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* In general, if you're adding or removing features from any of these, you
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* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
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* will store this name as part of the tags for the AGFI, so that later you can
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* reconstruct what is in a particular AGFI. These tags are also used to
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* determine which driver to build.
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*******************************************************************************/
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//*****************************************************************
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// Rocket configs, base off chipyard's RocketConfig
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//*****************************************************************
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// DOC include start: firesimconfig
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class FireSimRocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.RocketConfig)
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// DOC include end: firesimconfig
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class FireSimRocket1GiBDRAMConfig extends Config(
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++
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new FireSimRocketConfig)
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class FireSimRocketMMIOOnly1GiBDRAMConfig extends Config(
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++
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new FireSimRocketMMIOOnlyConfig)
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class FireSimRocket4GiBDRAMConfig extends Config(
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
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new FireSimRocketConfig)
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class FireSimRocketMMIOOnly4GiBDRAMConfig extends Config(
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
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new FireSimRocketMMIOOnlyConfig)
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class FireSimQuadRocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.QuadRocketConfig)
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//
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//// A stripped down configuration that should fit on all supported hosts.
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//// Flat to avoid having to reorganize the config class hierarchy to remove certain features
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//class FireSimSmallSystemConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithBootROM ++
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// new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
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// new chipyard.config.WithControlBusFrequency(3200.0) ++
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// new chipyard.config.WithSystemBusFrequency(3200.0) ++
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// new chipyard.config.WithFrontBusFrequency(3200.0) ++
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// new chipyard.config.WithMemoryBusFrequency(3200.0) ++
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// new WithoutClockGating ++
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// new WithoutTLMonitors ++
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// new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
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// new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
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// client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
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// phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32)
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// ))) ++
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// new testchipip.iceblk.WithBlockDevice ++
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// new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
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// new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
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// new chipyard.RocketConfig)
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//
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////*****************************************************************
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//// Boom config, base off chipyard's LargeBoomConfig
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////*****************************************************************
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//class FireSimLargeBoomConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new chipyard.LargeBoomConfig)
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//
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////********************************************************************
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//// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
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////********************************************************************
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//class FireSimLargeBoomAndRocketConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new chipyard.LargeBoomAndRocketConfig)
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//
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////******************************************************************
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//// Gemmini NN accel config, base off chipyard's GemminiRocketConfig
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////******************************************************************
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//class FireSimGemminiRocketConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new chipyard.GemminiRocketConfig)
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//
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//class FireSimLeanGemminiRocketConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new chipyard.LeanGemminiRocketConfig)
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//
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//class FireSimLeanGemminiPrintfRocketConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new chipyard.LeanGemminiPrintfRocketConfig)
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//
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////**********************************************************************************
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//// Supernode Configurations, base off chipyard's RocketConfig
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////**********************************************************************************
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//class SupernodeFireSimRocketConfig extends Config(
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// new WithFireSimHarnessClockBridgeInstantiator ++
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// new WithDefaultMemModel ++ // this is a global for all the multi-chip configs
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// new chipyard.harness.WithHomogeneousMultiChip(n=4, new Config(
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// new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8GB DRAM per node
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// new FireSimRocketConfig)))
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//
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////**********************************************************************************
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////* CVA6 Configurations
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////*********************************************************************************/
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//class FireSimCVA6Config extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new chipyard.CVA6Config)
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//
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////**********************************************************************************
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//// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations
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//// - Requires MTModels and MCRams mixins as prefixes to the platform config
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//// - May require larger build instances or JVM memory footprints
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////*********************************************************************************/
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//class FireSim16LargeBoomConfig extends Config(
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// new WithDefaultFireSimBridges ++
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// new WithDefaultMemModel ++
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// new WithFireSimConfigTweaks ++
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// new boom.common.WithNLargeBooms(16) ++
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// new chipyard.config.AbstractConfig)
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//
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class FireSimNoMemPortConfig extends Config(
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new WithDefaultFireSimBridges ++
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new freechips.rocketchip.subsystem.WithNoMemPort ++
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new testchipip.soc.WithMbusScratchpad ++
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new WithFireSimConfigTweaks ++
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new chipyard.RocketConfig)
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class FireSimRocketMMIOOnlyConfig extends Config(
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new WithDefaultMMIOOnlyFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.RocketConfig)
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class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config(
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new WithDefaultMMIOOnlyFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.LeanGemminiRocketConfig)
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class FireSimRadianceClusterSynConfig extends Config(
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new chipyard.harness.WithHarnessBinderClockFreqMHz(500.0) ++
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.RadianceClusterSynConfig)
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class FireSimQuadRocketSbusRingNoCConfig extends Config(
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new chipyard.config.WithNoTraceIO ++
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new WithDefaultFireSimBridges ++
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new WithFireSimConfigTweaks++
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new chipyard.QuadRocketSbusRingNoCConfig)
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class FireSimLargeBoomSV39CospikeConfig extends Config(
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new firesim.firesim.WithCospikeBridge ++
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks++
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new chipyard.config.WithSV39 ++
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new chipyard.LargeBoomV3Config)
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