Jerry Zhao 39092e9b00 Switch RTL-sim/FPGA/VLSI flows to chisel6

2024-05-13 12:48:06 -07:00

..

example-designs

fixing macro paths for yosys with circt generated verilog [skip ci]

2023-12-14 18:02:32 -08:00

hammer-mentor-plugins @ eca060af45

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

.gitignore

OpenROAD synthesis complete with fake rams on nangate45

2020-06-18 13:55:33 -07:00

env.yml

[skip ci] address comments, remove bwrc env vars, bump hammer

2019-09-26 15:40:22 -07:00

example-asap7.yml

renamed clock_clock to clock_uncore_clock

2023-06-30 15:04:38 -07:00

example-design.yml

renamed clock_clock to clock_uncore_clock

2023-06-30 15:04:38 -07:00

example-openroad.yml

use klayout for sky130-openroad tutorial, update conda install directions so that openroad/klayout installs don't fail

2023-06-08 14:56:42 -07:00

example-sky130.yml

fixing macro paths for yosys with circt generated verilog [skip ci]

2023-12-14 18:02:32 -08:00

example-tech.yml

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

example-tools.yml

[skip ci] add power-rtl and power-syn targets

2023-02-09 13:01:08 -08:00

example-vlsi

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

example-vlsi-sky130

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

Makefile

Switch RTL-sim/FPGA/VLSI flows to chisel6

2024-05-13 12:48:06 -07:00

power.mk

Rename timeout_cycles to TIMEOUT_CYCLES to match convention

2023-12-18 13:47:48 -08:00

sim.mk

Rename timeout_cycles to TIMEOUT_CYCLES to match convention

2023-12-18 13:47:48 -08:00

tutorial.mk

fixing macro paths for yosys with circt generated verilog [skip ci]

2023-12-14 18:02:32 -08:00

view_gds.py

view_gds.py update

2021-10-27 13:40:11 -07:00