43f6083b69
Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch
122 lines
4.7 KiB
Plaintext
122 lines
4.7 KiB
Plaintext
[submodule "rocket-chip"]
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path = generators/rocket-chip
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url = https://github.com/ucb-bar/rocket-chip.git
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[submodule "testchipip"]
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path = generators/testchipip
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url = https://github.com/ucb-bar/testchipip.git
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[submodule "barstools"]
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path = tools/barstools
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url = https://github.com/ucb-bar/barstools.git
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[submodule "tools/chisel3"]
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path = tools/chisel3
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url = https://github.com/freechipsproject/chisel3.git
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[submodule "tools/firrtl"]
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path = tools/firrtl
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url = https://github.com/freechipsproject/firrtl
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[submodule "tools/torture"]
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path = tools/torture
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url = https://github.com/ucb-bar/riscv-torture.git
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[submodule "generators/boom"]
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path = generators/boom
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url = https://github.com/riscv-boom/riscv-boom.git
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[submodule "generators/sifive-blocks"]
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path = generators/sifive-blocks
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url = https://github.com/sifive/sifive-blocks.git
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[submodule "generators/hwacha"]
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path = generators/hwacha
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url = https://github.com/ucb-bar/hwacha.git
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[submodule "sims/firesim"]
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path = sims/firesim
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url = https://github.com/firesim/firesim.git
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[submodule "generators/icenet"]
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path = generators/icenet
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url = https://github.com/firesim/icenet.git
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[submodule "generators/block-inclusivecache-sifive"]
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path = generators/sifive-cache
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url = https://github.com/ucb-bar/block-inclusivecache-sifive.git
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[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
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path = toolchains/riscv-tools/riscv-gnu-toolchain
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url = https://github.com/riscv/riscv-gnu-toolchain.git
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[submodule "toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt"]
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path = toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt
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url = https://github.com/ucb-bar/chipyard-toolchain-prebuilt.git
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shallow = true
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[submodule "toolchains/riscv-tools/riscv-isa-sim"]
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path = toolchains/riscv-tools/riscv-isa-sim
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url = https://github.com/riscv/riscv-isa-sim.git
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[submodule "toolchains/riscv-tools/riscv-pk"]
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path = toolchains/riscv-tools/riscv-pk
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url = https://github.com/riscv/riscv-pk.git
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[submodule "toolchains/riscv-tools/riscv-tests"]
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path = toolchains/riscv-tools/riscv-tests
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url = https://github.com/riscv/riscv-tests.git
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[submodule "toolchains/riscv-tools/riscv-openocd"]
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path = toolchains/riscv-tools/riscv-openocd
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url = https://github.com/riscv/riscv-openocd.git
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[submodule "toolchains/esp-tools/riscv-gnu-toolchain"]
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path = toolchains/esp-tools/riscv-gnu-toolchain
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url = https://github.com/ucb-bar/esp-gnu-toolchain.git
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[submodule "toolchains/esp-tools/riscv-isa-sim"]
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path = toolchains/esp-tools/riscv-isa-sim
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url = https://github.com/ucb-bar/esp-isa-sim.git
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[submodule "toolchains/esp-tools/riscv-pk"]
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path = toolchains/esp-tools/riscv-pk
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url = https://github.com/riscv/riscv-pk.git
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[submodule "toolchains/esp-tools/riscv-tests"]
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path = toolchains/esp-tools/riscv-tests
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url = https://github.com/ucb-bar/esp-tests.git
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[submodule "toolchains/libgloss"]
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path = toolchains/libgloss
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url = https://github.com/ucb-bar/libgloss-htif.git
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[submodule "vlsi/hammer"]
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path = vlsi/hammer
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url = https://github.com/ucb-bar/hammer.git
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[submodule "tools/dsptools"]
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path = tools/dsptools
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url = https://github.com/ucb-bar/dsptools.git
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[submodule "tools/chisel-testers"]
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path = tools/chisel-testers
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url = https://github.com/freechipsproject/chisel-testers.git
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[submodule "tools/treadle"]
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path = tools/treadle
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url = https://github.com/freechipsproject/treadle.git
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[submodule "generators/sha3"]
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path = generators/sha3
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url = https://github.com/ucb-bar/sha3.git
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[submodule "tools/firrtl-interpreter"]
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path = tools/firrtl-interpreter
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url = https://github.com/freechipsproject/firrtl-interpreter.git
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[submodule "vlsi/hammer-cadence-plugins"]
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path = vlsi/hammer-cadence-plugins
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url = https://github.com/ucb-bar/hammer-cadence-plugins.git
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[submodule "vlsi/hammer-synopsys-plugins"]
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path = vlsi/hammer-synopsys-plugins
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url = https://github.com/ucb-bar/hammer-synopsys-plugins.git
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[submodule "vlsi/hammer-mentor-plugins"]
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path = vlsi/hammer-mentor-plugins
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url = https://github.com/ucb-bar/hammer-mentor-plugins.git
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[submodule "toolchains/qemu"]
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path = toolchains/qemu
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url = https://github.com/qemu/qemu.git
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[submodule "tools/axe"]
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path = tools/axe
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url = https://github.com/CTSRD-CHERI/axe.git
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[submodule "software/spec2017"]
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path = software/spec2017
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url = https://github.com/ucb-bar/spec2017-workload.git
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[submodule "software/coremark"]
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path = software/coremark
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url = https://github.com/ucb-bar/coremark-workload.git
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[submodule "generators/gemmini"]
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path = generators/gemmini
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url = https://github.com/ucb-bar/gemmini
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[submodule "software/firemarshal"]
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path = software/firemarshal
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url = https://github.com/firesim/FireMarshal.git
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[submodule "generators/ariane"]
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path = generators/ariane
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url = https://github.com/ucb-bar/ariane-wrapper.git
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[submodule "tools/DRAMSim2"]
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path = tools/DRAMSim2
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url = https://github.com/firesim/DRAMSim2.git
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