3f5a204fd0
* [uart] add uart adapter | add uart + adapter to all configs * [uart] change pty define name | add uart to all configs that need it * [uart] default to 115200 baudrate * [dromajo] first working commit * [dromajo] bump boom for commit-width > 1 fix * [dromajo] adjust dromajo commits * [dromajo] bump boom * commit dromajo changes * extra * [dromajo] add block device to configs * rebump older modules * bump firesim * [chipyard] enable dromajo in midas level simulation * [testchipip] forgot to bump * get rid of breaking things * bump firesim * bump boom * Bump BOOM to ifu3 WIP * bump firesim * fix how memory is passed to dromajo * bump boom and firesim * fix merge issues * add dromajo cosim bridge in chipyard * move traceio back into testchipip (#488) * refer to testchipip traceio in firechip (#490) * Move TraceIO fragment to chipyard (#492) * fix chipyard dromajo bridge (#493) * Sboom dromajo bump (#501) * [FireChip] Use clock in BridgeBinders * [firesim] Update TraceGen BridgeBinder * [Firechip] Add support for Tile <-> Uncore rational division * [firesim] Update the multiclock test * [firechip] Commit some Eagle X-related mock configs * [firechip] Instantiate multiple TracerV bridges * [Firechip] Include reset in tracerv tokens * [TracerV] Drop the first token in comparison tests * [Firechip] Make reverse instruction order in trace printf * WARNING: Point at a fork of boom @ davidbiancolin * [firesim] Update ClockBridge API * Add Gemmini to README [ci skip] (#487) * [firechip] Isolate all firesim-multiclock stuff in a single file * add documentation on ring network and system bus * Bump firesim for CI * Bump FireSim * Bump testchipip to dev [ci skip] * Bump FireSim * [make] split up specific make vars/targets into frags (#499) * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder * [dromajo] add dromajo * [dromajo] bump for new traceio changes * bump firesim * bump firesim * point to chipyard traceio * bump boom Co-authored-by: David Biancolin <david.biancolin@gmail.com> Co-authored-by: Howard Mao <zhehao.mao@gmail.com> * Support Dromajo + TracerV configurations * [docs] add documentation for Dromajo in FireSim + Chipyard * add a bit more docs * [docs] bump docs * [firesim] dump artefacts in firesim * [firesim] update firesim * [testchipip] remove extraneous items in testchipip * [dromajo] prevent dromajo from breaking when params unset * update firesim, dromajo, and testchipip * [firesim] bump firesim * [firesim] bump firesim * [misc] bump firesim and testchipip for reviewer comments * remove WithNoGPIO fragment * bump firesim * bump dromajo boom config * bump firesim * generate artefacts in firesim testsuite Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com> Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu> Co-authored-by: David Biancolin <david.biancolin@gmail.com> Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
125 lines
4.8 KiB
Plaintext
125 lines
4.8 KiB
Plaintext
[submodule "rocket-chip"]
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path = generators/rocket-chip
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url = https://github.com/ucb-bar/rocket-chip.git
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[submodule "testchipip"]
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path = generators/testchipip
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url = https://github.com/ucb-bar/testchipip.git
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[submodule "barstools"]
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path = tools/barstools
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url = https://github.com/ucb-bar/barstools.git
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[submodule "tools/chisel3"]
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path = tools/chisel3
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url = https://github.com/freechipsproject/chisel3.git
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[submodule "tools/firrtl"]
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path = tools/firrtl
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url = https://github.com/freechipsproject/firrtl
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[submodule "tools/torture"]
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path = tools/torture
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url = https://github.com/ucb-bar/riscv-torture.git
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[submodule "generators/boom"]
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path = generators/boom
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url = https://github.com/riscv-boom/riscv-boom.git
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[submodule "generators/sifive-blocks"]
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path = generators/sifive-blocks
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url = https://github.com/sifive/sifive-blocks.git
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[submodule "generators/hwacha"]
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path = generators/hwacha
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url = https://github.com/ucb-bar/hwacha.git
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[submodule "sims/firesim"]
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path = sims/firesim
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url = https://github.com/firesim/firesim.git
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[submodule "generators/icenet"]
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path = generators/icenet
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url = https://github.com/firesim/icenet.git
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[submodule "generators/block-inclusivecache-sifive"]
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path = generators/sifive-cache
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url = https://github.com/sifive/block-inclusivecache-sifive.git
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[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
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path = toolchains/riscv-tools/riscv-gnu-toolchain
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url = https://github.com/riscv/riscv-gnu-toolchain.git
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[submodule "toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt"]
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path = toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt
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url = https://github.com/ucb-bar/chipyard-toolchain-prebuilt.git
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shallow = true
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[submodule "toolchains/riscv-tools/riscv-isa-sim"]
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path = toolchains/riscv-tools/riscv-isa-sim
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url = https://github.com/riscv/riscv-isa-sim.git
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[submodule "toolchains/riscv-tools/riscv-pk"]
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path = toolchains/riscv-tools/riscv-pk
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url = https://github.com/riscv/riscv-pk.git
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[submodule "toolchains/riscv-tools/riscv-tests"]
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path = toolchains/riscv-tools/riscv-tests
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url = https://github.com/riscv/riscv-tests.git
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[submodule "toolchains/riscv-tools/riscv-openocd"]
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path = toolchains/riscv-tools/riscv-openocd
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url = https://github.com/riscv/riscv-openocd.git
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[submodule "toolchains/esp-tools/riscv-gnu-toolchain"]
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path = toolchains/esp-tools/riscv-gnu-toolchain
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url = https://github.com/ucb-bar/esp-gnu-toolchain.git
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[submodule "toolchains/esp-tools/riscv-isa-sim"]
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path = toolchains/esp-tools/riscv-isa-sim
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url = https://github.com/ucb-bar/esp-isa-sim.git
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[submodule "toolchains/esp-tools/riscv-pk"]
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path = toolchains/esp-tools/riscv-pk
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url = https://github.com/riscv/riscv-pk.git
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[submodule "toolchains/esp-tools/riscv-tests"]
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path = toolchains/esp-tools/riscv-tests
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url = https://github.com/ucb-bar/esp-tests.git
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[submodule "toolchains/libgloss"]
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path = toolchains/libgloss
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url = https://github.com/ucb-bar/libgloss-htif.git
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[submodule "vlsi/hammer"]
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path = vlsi/hammer
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url = https://github.com/ucb-bar/hammer.git
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[submodule "tools/dsptools"]
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path = tools/dsptools
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url = https://github.com/ucb-bar/dsptools.git
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[submodule "tools/chisel-testers"]
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path = tools/chisel-testers
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url = https://github.com/freechipsproject/chisel-testers.git
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[submodule "tools/treadle"]
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path = tools/treadle
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url = https://github.com/freechipsproject/treadle.git
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[submodule "generators/sha3"]
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path = generators/sha3
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url = https://github.com/ucb-bar/sha3.git
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[submodule "tools/firrtl-interpreter"]
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path = tools/firrtl-interpreter
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url = https://github.com/freechipsproject/firrtl-interpreter.git
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[submodule "vlsi/hammer-cadence-plugins"]
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path = vlsi/hammer-cadence-plugins
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url = https://github.com/ucb-bar/hammer-cadence-plugins.git
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[submodule "vlsi/hammer-synopsys-plugins"]
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path = vlsi/hammer-synopsys-plugins
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url = https://github.com/ucb-bar/hammer-synopsys-plugins.git
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[submodule "vlsi/hammer-mentor-plugins"]
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path = vlsi/hammer-mentor-plugins
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url = https://github.com/ucb-bar/hammer-mentor-plugins.git
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[submodule "toolchains/qemu"]
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path = toolchains/qemu
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url = https://github.com/qemu/qemu.git
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[submodule "tools/axe"]
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path = tools/axe
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url = https://github.com/CTSRD-CHERI/axe.git
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[submodule "software/spec2017"]
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path = software/spec2017
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url = https://github.com/ucb-bar/spec2017-workload.git
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[submodule "software/coremark"]
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path = software/coremark
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url = https://github.com/ucb-bar/coremark-workload.git
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[submodule "generators/gemmini"]
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path = generators/gemmini
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url = https://github.com/ucb-bar/gemmini
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[submodule "software/firemarshal"]
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path = software/firemarshal
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url = https://github.com/firesim/FireMarshal.git
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[submodule "generators/ariane"]
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path = generators/ariane
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url = https://github.com/ucb-bar/ariane-wrapper.git
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[submodule "tools/DRAMSim2"]
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path = tools/DRAMSim2
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url = https://github.com/firesim/DRAMSim2.git
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[submodule "tools/dromajo/dromajo-src"]
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path = tools/dromajo/dromajo-src
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url = https://github.com/abejgonzalez/dromajo.git
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