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* [ariane/make] integrate ariane | have verilator be installed on path not in makefile * [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore * [firesim] bump * [ci] add midas ariane tests * [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments * [ci] remove references to local verilator install * [verilator] update flags * [verilator] minimal set of flags for ariane * [ariane] bump ariane to master * [ci] revert to 4.016 verilator * [ci] install verilator to ci server | misc compile fixes * [ci/make] add longer ci timeout | update when assert is added in verilator sim * [firesim] bump for misc. updates * [make/ci] cleanup makefile and remove firesim tests of it * [docs/firesim] bump and clean docs * [firesim] bump * [ci] use remote verilator for midas tests * [misc] cleanup built.sbt more * [firesim] bump * [misc] bump build.sbt patch for tutorials * [firesim/ci] cleanup and bump firesim
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15 lines
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Ariane Core
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====================================
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`Ariane <https://github.com/pulp-platform/ariane>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
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The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`.
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The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
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.. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
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While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters).
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.. Warning:: This target does not support Verilator simulation at this time. Please use VCS.
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For more information, please refer to the `GitHub repository <https://github.com/pulp-platform/ariane>`__.
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