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* [nvdla] initial nvdla integration * [nvdla] add firesim configs * [nvdla] re-add accidentally deleted line * [nvdla] works on master with small * [nvdla] use master branch of nvdla * [nvdla] remove extra sources * [nvdla] bump * [nvdla + ariane] bump and use insert-includes for pre-processing * [nvdla] add ci | remove target configs in FireChip | update naming * [nvdla] bump nvdla | fix ci run-tests error * [nvdla] re-enable PCWM-L error | fix/update makefile(s) * [nvdla] bump nvdla fragments in FireChip * [misc] bump tutorial patches * [chipyard] remove extra import * [nvdla] bump nvdla for pbus [ci skip] * [nvdla] update firemarshal and add nvdla workload * [nvdla] bump nvdla-workload * [nvdla] bump hw * [docs] add basic documentation * [docs] adjustments to documentation * [misc] update docs | bump firesim with recipe * [misc] disable error on warnings in verilator | bump number width to match RC * [docs] fix doc build error * [verilator] move no fail on warning to be global * [ci skip] [nvdla] bump submodule urls * [misc] move firesim specific configs into nvdla dir [ci skip] * [nvdla] fix run-tests in ci * update RC configs | bump marshal | bump nvdla-workload * [nvdla] bump nvdla-workload [ci skip] * add topology mixin to nvdla configs * update tutorial patches
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.. _generator-index:
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Included RTL Generators
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============================
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A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL.
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This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`).
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A standard RTL design is essentially just a single instance of a design coming from a generator.
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However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways.
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The following pages introduce the generators integrated with the Chipyard framework.
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Chipyard bundles the source code for the generators, under the ``generators/`` directory.
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It builds them from source each time (although the build system will cache results if they have not changed),
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so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows.
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.. toctree::
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:maxdepth: 2
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:caption: Generators:
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Rocket-Chip
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Rocket
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BOOM
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Hwacha
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Gemmini
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IceNet
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TestChipIP
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SiFive-Generators
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SHA3
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Ariane
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NVDLA
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